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PDF MC74AC4040 Data sheet ( Hoja de datos )

Número de pieza MC74AC4040
Descripción 12-Stage Binary Ripple Counter
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No Preview Available ! MC74AC4040 Hoja de datos, Descripción, Manual

MC74AC4040
12-Stage Binary Ripple
Counter
The MC74AC4040 consists of 12 master-slave flip-flops. The
output of each flip-flop feeds the next and the frequency at each output
is half that of the preceding one. The state of the counter advances on
the negative-going edge of the Clock input. Reset is asynchronous and
active-high.
State changes of the Q outputs do not occur simultaneously because
of internal ripple delays. Therefore, decoded output signals are subject
to decoding spikes and may have to be gated with the Clock of the
MC74AC4040 for some designs.
Features
140 MHz Typ. Clock
Outputs Source/Sink 24 mA
Operating Voltage Range: 2.0 to 6.0 V
High Noise Immunity
These are Pb−Free Devices
VCC Q11 Q10 Q8
16 15 14 13
Q9 RESET CLK Q1
12 11 10 9
www.onsemi.com
16
1
MARKING
DIAGRAM
16
SOIC−16
D SUFFIX
CASE 751B
1
AC4040G
AWLYWW
A = Assembly Location
WL = Wafer Lot
Y = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
12345678
Q12 Q6 Q5 Q7 Q4 Q3 Q2 GND
Figure 1. Pinout: 16−Lead Packages Conductors
(Top View)
FUNCTION TABLE
Clock Reset
L
L
XH
Output State
No Change
Advance to next state
All Outputs are low
© Semiconductor Components Industries, LLC, 2015
March, 2015 − Rev. 8
1
Publication Order Number:
MC74AC4040/D

1 page




MC74AC4040 pdf
MC74AC4040
AC CHARACTERISTICS (For Figures and Waveforms − See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC
74AC
Symbol
Parameter
VCC*
(V)
TA = +25°C
CL = 50 pF
Min Typ Max
TA = −40°C to +85°C
CL = 50 pF
Min Max
Unit
Fig. No.
Maximum Clock
fmax Frequency
3.3 110 120
5.0 130 140
100
120
MHz
nCP to Q1
Propagation Delay
nCP to Q1
Propagation Delay
Qn to Qn +1 Qn to Qn +1
MR to Q
tHL
Propagation Delay
MR to Q
trec
nCP to MR
Recovery Time
tw nCP
Minimum Pulse Width
Clock Pin
tw MR
Minimum Pulse Width
Master Reset
*Voltage Range 3.3 V is 3.3 V ±0.3 V.
*Voltage Range 5.0 V is 5.0 V ±0.5 V.
3.3 2.0 − 11
5.0 2.0 − 8.0
3.3 0
5.0 0
− 5.5
− 3.5
3.3 3.0 − 12
5.0 3.0 − 10
3.3 0 −2.5 −
5.0 0 −1.5 −
3.3 4.0 3.5
5.0 3.0 2.5
3.3 4.0 3.5
3.0 3.0 2.5
2.0
2.0
0
0
3.0
3.0
0
0
4.5
3.5
4.5
3.5
14
10 ns
6.5
4.5 ns
15
12 ns
ns
ns
ns
CAPACITANCE
Symbol
Parameter
CIN Input Capacitance
CPD Power Dissipation Capacitance
Value
Typ
4.5
50
Unit
pF
pF
Test Conditions
VCC = 5.0 V
VCC = 5.0 V
ORDERING INFORMATION
Part Number
Package
Shipping
MC74AC4040DG
SOIC−16
(Pb−Free)
48 Units / Rail
MC74AC4040DR2G
SOIC−16
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
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