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PDF PDSP16116 Data sheet ( Hoja de datos )

Número de pieza PDSP16116
Descripción 16 by 16 Bit Complex Multiplier
Fabricantes Zarlink Semiconductor 
Logotipo Zarlink Semiconductor Logotipo



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No Preview Available ! PDSP16116 Hoja de datos, Descripción, Manual

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PDSP1P6D1S1P166/1A16//AM/MCC
16 by 16 Bit Complex Multiplier
The PDSP16116A will multiply two complex (16 + 16) bit
words every 50ns and can be configured to output the
complete complex (32 + 32) bit result within a single cycle. The
data format is fractional two's complement.
The PDSP16116/A contains four 16 x 16 Array Multipliers,
two 32 bit Adder/Subtractors and all the control logic required
to support Block Floating Point Arithmetic as used in FFT
applications. In combination with a PDSP16318, the
PDSP16116A forms a two chip 10MHz Complex Multiplier
Accumulator with 20 bit accumulator registers and output
shifters. The PDSP16116 in combination with two
PDSP16318s and two PDSP1601s forms a complete 10MHz
Radix 2 DIT FFT Butterfly solution which fully supports Block
Floating Point Arithmetic. The PDSP16116/A has an
extremely high throughput that is suited to recursive
algorithms as all calculations are performed with a single
pipeline delay (two cycle fall-through).
FEATURES
s Complex Number (16 + 16) X (16 + 16) Multiplication
s Full 32 bit Result
s 20MHz Clock Rate
s Block Floating Point FFT Butterfly Support
s -1 times -1 Trap
s Two's Complement Fractional Arithmetic
s TTL Compatible I/O
s Complex Conjugation
s 2 Cycle Fall Through
s 144 pin PGA or QFP packages
APPLICATION
s Fast Fourier Transforms
s Digital Filtering
s Radar and Sonar Processing
s Instrumentation
s Image Processing
ASSOCIATED PRODUCTS
PDSP16318/A
PDSP16112/A
PDSP16330/A
PDSP1601/A
PDSP16350
PDSP16256
PDSP16510
Complex Accumulator
(16 + 16) X (12 + 12) Complex Multiplier
Pythagoras Processor
ALU and Barrel Shifter
Precision Digital Modulator
Programmable FIR Filter
Single Chip FFT Processor
DS3858
ISSUE 3.0
June 2000
Ordering Information
PDSP16116 MC GC1R 10MHz MIL-883 screened -
ceramic QFP
PDSP16116 MC AC1R 10MHz MIL-883 screened -
PGA package
PDSP16116A MC GC1R 20MHz MIL-883 screened -
ceramic QFP
PDSP16116A MC AC1R20MHz MIL-883 screened -
PGA package
XR
REG
XI
REG
YR
REG
YI
REG
MULT
MULT
MULT
MULT
REG
REG
REG
REG
+/- +/-
SHIFT
SHIFT
REG
REG
PR PI
Fig.1 Simplified Block Diagram
CHANGE NOTIFICATION
The change notification requirements of MIL-M-38510 will be
implemented on this device type. Known customers will be
notified of any changes since last buy when ordering further
parts if significant changes have been made.
Rev
Date
AB C
JULY 1993 OCT 1998 JUN 2000
D
1

1 page




PDSP16116 pdf
PDSP16116/A/MC
GC AC Signal GC AC Signal GC AC Signal GC
1 D3 PI14 37
2 C2 PI15 38
3 B1 WTOUT1 39
4 D2 WTOUT0 40
5 E3 SFTR0 41
6 C1 SFTR1 42
7 E2 SFTR2 43
8 D1 OEI 44
9 F2 CONX 45
10 F3 CONY 46
11 E1 ROUND 47
12 G2 AI13 48
13 G3 AI14 49
14 F1 AI15 50
15 G1 AR13 51
16 H2 AR14 52
17 H1 AR15 53
18 H3 YI15 54
19 J3 YI14 55
20 J1 YI13 56
21 K1 YI12 57
22 J2 YI11 58
23 K2 YI10 59
24 K3 YI9 60
25 L1 YI8 61
26 L2 YI7 62
27 M1 YI6 63
28 N1 YI5 64
29 M2 YI4 65
30 L3 YI3 66
31 N2 YI2 67
32 P1 YI1 68
33 M3 YI0 69
34 N3 XI0 70
35 B2 GND 71
36 A1 VDD 72
NOTE. All GND and VDD pins must be used
N4 XI1 73 P2 GND 109
P3 XI2 74 R1 VDD 110
R2 XI3 75 P15 YR12 111
P4 XI4 76 M14 YR11 112
N5 XI5 77 L13 YR10 113
R3 XI6 78 N15 YR9 114
P5 XI7 79 L14 YR8 115
R4 XI8 80 M15 YR7 116
N6 XI9 81 K13 YR6 117
P6 XI10 82 K14 YR5 118
R5 XI11 83 L15 YR4 119
P7 XI12 84 J14 YR3 120
N7 XI13 85 J13 YR2 121
R6 XI14 86 K15 YR1 122
R7 XI15 87 J15 YR0 123
P8 CEY 88 H14 EOPSS 124
R8 CEX 89 H15 VDD 125
N8 XR15 90 H13 SOBFP 126
N9 XR14 91 G13 WTB1 127
R9 XR13 92 G15 WTB0 128
R10 XR12 93 F15 WTA1 129
P9 XR11 94 G14 WTA0 130
P10 XR10 95 F14 MBFP 131
N10 XR9 96 F13 CLK 132
R11 XR8 97 E15 OSEL1 133
P11 XR7 98 E14 OSEL0 134
R12 XR6 99 D15 OER 135
R13 XR5 100 C15 SFTA0 136
P12 XR4 101 D14 SFTA1 137
N11 XR3 102 E13 GWR0 138
P13 XR2 103 C14 GWR1 139
R14 XR1 104 B15 GWR2 140
N12 XR0 105 D13 GWR3 141
N13 YR15 106 C13 GWR4 142
P14 YR14 107 B14 PR15 143
R15 YR13 108 A15 PR14 144
Figure 3A - Pin connections for AC144 (Power) and GC144 packages
AC
N14
M13
A14
B12
C11
A13
B11
A12
C10
B10
A11
B13
C12
A10
A9
B8
A8
C8
C7
A7
A6
B7
B6
C6
A5
B5
A4
A3
B4
C5
B3
A2
C4
C3
B9
C9
Signal
VDD
GND
PR13
PR12
PR11
PR10
PR9
PR8
PR7
PR6
PR5
GND
VDD
PR4
PR3
PR2
PR1
PR0
PI0
PI1
PI2
PI3
PI4
VDD
PI5
GND
PI6
PI7
PI8
PI9
PI10
PI11
PI12
PI13
GND
VDD
5

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PDSP16116 arduino
In normal mode, these inputs perform a different function.
They directly control the internal shifter at the output port as
shown in Table 7.
WTB1:0 FUNCTION
11 shift complex product one place to the left
00 no shift applied
01 shift complex product one place to the right
10 shift complex product two places to the right
Table 7 - Normal Mode Shift Control
SFTA1:0 (BFP & NORMAL MODES)
In BFP mode, these signals act as as the A-word shift
control. They allow shifting from one to four places to the right,
see Table 8. Depending on the relative weightings of the A-
words and the complex product, the A-word may have to be
shifted to the right to ensure compatible weightings at the
inputs to the PDSP16318 complex accumulator. (The two
words must have the same weighting if they are to be added).
In normal mode, SFTA0 performs a different a different
function. If WTB1:0 is set to implement a left shift, then
overflow will occur if the data is fully 32 bits wide. This pin is
used to flag such an overflow. SFTA1 is not used in normal
mode.
WTB1:0 FUNCTION
0 0 Shift A-word 1 places to the right
0 1 Shift A-word 2 places to the right
1 0 Shift A-word 3 places to the right
1 1 Shift A-word 4 places to the right
Table 8 - External A-word shift control
OSEL1:0
The outputs from the device are selected by the OSEL0 &
OSEL1 instruction bits. These controls allow selection of the
output combination during the current cycle. (They are not
registered). These are four possible output configurations
that allow either complex outputs of the most or least
significant bytes, or real or imaginary outputs of the full 32 bit
word (see Table 4). OSEL0 and OSEL1 should both be tied
low when in BFP mode.
BFP MODE FFT APPLICATION
The PDSP16116 may be used as the main arithmetic unit
of the butterfly processor which will allow the following FFT
benchmarks:
1024 point complex radix-2 transform in 517us
512 point complex radix-2 transform in 235us
256 point complex radix-2 transform in 106us
In addition, with pin MBFP tied high, the BFP circuitry
within the PDSP16116 can be used to adaptively rescale data
throughout the course of the FFT so as to give high-resolution
results.
The BFP system on the PDSP16116 can be used with any
variation of the Radix-2 Decimation-In-Time FFT - e.g. the
PDSP16116/A/MC
Constant Geometry algorithm, the In-Place algorithm etc. An
N-point Radix-2 DIT FFT is split into log (N) passes. Each pass
consists of N/2 ‘butterflies’, each performing the operation:
A’ = A + B.W
B’ = A - B.W
Where W is the complex coefficient and A & B are the complex
data.
Fig.4 illustrates how a single PDSP16116 may be
combined with two PDSP1601’s and two PDSP16318’s to
form a complete BFP butterfly processor. The PDSP16318’s
are used to perform the complex addition and subtraction of
the butterfly operation, while the PDSP1601’s are used to
match the data path of the A-word to the pipelining and shifting
operations within the PDSP16116.
For more information on the theory and construction of this
butterfly processor, refer to application note AN59.
BFP MODE OPERATION
The BFP mode on the PDSP16116 is intended for use in
the FFT application described above. i.e. it is intended to
prevent data degredation during the course of an FFT
calculation. The operation of the PDSP16116 based BFP
butterfly processor (see Fig.4) is described below.
The Block Floating Point System
A block floating point system is essentially an ordinary
integer arithmetic system with some clever logic bolted on.
The object of the extra logic is to lend the system some of the
enormous dynamic range afforded by a true floating point
system without suffering the corresponding loss in
performance.
The initial data used by the FFT should all have the same
binary arithmetic weighting. i.e. the binary point should
occupy the same position in every data word, as is normal in
integer arithmetic. However, during the course of the FFT, a
variety of weightings are used in the data words to increase the
dynamic range available. This situation is similar to that within
a true floating point system, though the range of numbers
representable is more limited. In the BFP system used in the
PDSP16116, there are, within any one pass of the FFT, four
possible positions of the binary point wihin the integer words.
To record the position of its binary point, each word has a 2-
bit word tag associated with it. By way of example, in a
particular pass we may have the following four positions of
binary point avaiable, each denoted by a certain value of word
tag:
XX.XXXXXXXXXXXX
XXX.XXXXXXXXXXX
XXXX.XXXXXXXXXX
XXXXX.XXXXXXXXX
word tag = 00
word tag = 01
word tag = 10
word tag = 11
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