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PDF NAND04GA3C2A Data sheet ( Hoja de datos )
| Número de pieza | NAND04GA3C2A | |
| Descripción | (NAND04GA3C2A / NAND04GW3C2A) Multi-level NAND Flash Memory | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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NAND04GA3C2A
NAND04GW3C2A
4Gbit, 2112 Byte Page, 3V, Multi-level NAND Flash Memory
Features
■ High density multi-level Cell (MLC) NAND
Flash memories:
– Up to 128 Mbit spare area
– Cost effective solutions for mass storage
applications
■ NAND interface
– x8 bus width
– Multiplexed Address/ Data
■ Supply voltages
– VDD = 2.7 to 3.6V core supply voltage for
Program, Erase and Read operations.
– VDDQ = 1.7 to 1.95 or 2.7 to 3.6V for I/O
buffers.
■ Page size: (2048 + 64 spare) Bytes
■ Block size: (256K + 8K spare) Bytes
■ Page Read/Program
– Random access: 60µs (max)
– Sequential access: 60ns(min)
– Page Program Operation time: 800µs (typ)
■ Cache Read mode
– Internal Cache Register to improve the
read throughput
■ Fast Block Erase
– Block erase time: 1.5ms (typ)
■ Status Register
■ Electronic Signature
■ Serial Number option
Table 1. Product List
Reference
Part Number
NAND04Gx3C2A
NAND04GA3C2A
NAND04GW3C2A
TSOP48 12 x 20mm
■ Chip Enable ‘don’t care’
– for simple interface with microcontroller
■ Data Protection
– Hardware Program/Erase locked during
power transitions
■ Embedded Error Correction Code (ECC)
– Internal ECC accelerator
– Easy ECC Command Interface
■ Data integrity
– 10,000 Program/Erase cycles (with ECC)
– 10 years Data Retention
■ ECOPACK® package available
■ Development tools
– Bad Blocks Management and Wear
Leveling algorithms
– File System OS Native reference software
– Hardware simulation models
Density
4 Gbits
November 2006
Rev 2
1/51
www.st.com
1
1 page  
NAND04GA3C2A, NAND04GW3C2A
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Address insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Address Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Electronic Signature Byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Electronic Signature Byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Block Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Program, Erase Times and Program Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . . 33
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DC Characteristics, VDDQ 3V Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AC Characteristics for Command, Address, Data Input, VDDQ 3V Devices . . . . . . . . . . . 37
AC Characteristics for Operations, VDDQ 3V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data. . . 48
Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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5 Page 
NAND04GA3C2A, NAND04GW3C2A
2 Memory array organization
2 Memory array organization
The memory array is made up of NAND structures where 32 cells are connected in series.
The memory array is organized in blocks where each block contains 128 pages. The array is
split into two areas, the main area and the spare area. The main area of the array is used to
store data whereas the spare area is typically used to store software flags or Bad Block
identification.
The pages are split into a 2048 Byte main area and a spare area of 64 Bytes.Refer to
Figure 4: Memory Array Organization.
2.1 Bad blocks
The NAND04GA3C2A and NAND04GW3C2A devices may contain Bad Blocks, that is
blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional
Bad Blocks may develop during the lifetime of the device.
The Bad Block Information is written prior to shipping (refer to Section 9.1: Bad block
management for more details).
Table 4: Valid Blocks shows the minimum number of valid blocks in each device. The values
shown include both the Bad Blocks that are present when the device is shipped and the Bad
Blocks that could develop later on.
These blocks need to be managed using Bad Blocks Management and Block Replacement
(refer to Section 9: Software algorithms).
Table 4.
Valid Blocks
Density of Device
4 Gbits
Min
2008
Max
2048
11/51
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