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PDF VIPER100-E Data sheet ( Hoja de datos )

Número de pieza VIPER100-E
Descripción SMPS PRIMARY I.C.
Fabricantes ST Microelectronics 
Logotipo ST Microelectronics Logotipo



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No Preview Available ! VIPER100-E Hoja de datos, Descripción, Manual

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VIPer100-E
SMPS PRIMARY I.C.
General Features
Type
VIPer100-E
VDSS
620V
In RDS(on)
3 A 2.5
ADJUSTABLE SWITCHING FREQUENCY UP
TO 200 kHz
CURRENT MODE CONTROL
SOFT START AND SHUTDOWN CONTROL
AUTOMATIC BURST MODE OPERATION IN
STAND-BY CONDITION ABLE TO MEET
“BLUE ANGEL” NORM (<1w TOTAL POWER
CONSUMPTION)
INTERNALLY TRIMMED ZENER
REFERENCE
UNDERVOLTAGE LOCK-OUT WITH
HYSTERESIS
INTEGRATED START-UP SUPPLY
OVER-TEMPERATURE PROTECTION
LOW STAND-BY CURRENT
ADJUSTABLE CURRENT LIMITATION
Block Diagram
PENTAWATT HV
PENTAWATT HV (022Y)
Description
VIPer100-E, made using VIPower M0 Technology,
combines on the same silicon chip a state-of-the-
art PWM circuit together with an optimized, high
voltage, Vertical Power MOSFET (620V/ 3A).
Typical applications cover offline power supplies
with a secondary power capability of 50W in wide
range condition and 100W in single range or with
doubler configuration. It is compatible from both
primary or secondary regulation loop despite
using around 50% less components when
compared with a discrete solution. Burst mode
operation is an additional feature of this device,
offering the ability to operate in stand-by mode
without extra components.
OSC
ON/OFF
OSCILLATOR
SECURITY PWM
LATCH
LATCH
VDD
UVLO
LOGIC
R/S FF Q
S
S
R1 FF Q
R2 R3
OVERTEMP.
DETECTOR
0.5 V +
_
ERROR
_ AMPLIFIER
13 V +
4.5 V
1.7 µ s
DELAY
September 2005
250 ns
BLANKING
COMP
DRAIN
0.5V
++ _
_
1 V/A
CURRENT
AMPLIFIER
SOURCE
Rev 1
1/29
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1 page




VIPER100-E pdf
VIPer100-E
1 Electrical Data
1.2 Electrical Characteristics
TJ = 25°C; VDD = 13V, unless otherwise specified
Table 2. Power Section
Symbol
Parameter
Test Conditions
Min Typ Max Unit
BVDS Drain-Source Voltage ID = 1mA; VCOMP = 0V
620
V
IDSS
Off-State Drain
Current
VCOMP = 0V; Tj = 125°C
VDS = 620V
1 mA
RDS(on) Static Drain-Source
On Resistance
ID = 2A
ID = 2A; Tj = 100°C
2.3 2.5
4.5
tf Fall Time
ID = 0.2A; VIN =300V (1)Figure 7
100
ns
tr Rise Time
ID = 0.4A; VIN = 300V (1)Figure 7
50
ns
Coss
Output Capacitance VDS = 25V
150 pF
(1) On Inductive Load, Clamped.
Table 3. Supply Section
Symbol
Parameter
IDDch Start-Up Charging Current
IDD0 Operating Supply Current
IDD1 Operating Supply Current
VDDoff
VDDon
VDDhyst
Undervoltage Shutdown
Undervoltage Reset
Hysteresis Start-up
Table 4. Oscillator Section
Symbol
Parameter
FSW
Oscillator Frequency Total
Variation
VOSCIH
VOSCIL
Oscillator Peak Voltage
Oscillator Valley Voltage
Test Conditions
VDD = 5V; VDS = 35V
(see Figure 6)(see Figure 11)
VDD = 12V; FSW = 0kHz
(see Figure 6)
VDD = 12V; Fsw = 100kHz
VDD = 12V; Fsw = 200kHz
(see Figure 6)
(see Figure 6)
(see Figure 6)
Min
7.5
2.4
Test Conditions‘
RT=8.2K; CT=2.4nF
VDD=9 to 15V;
with RT± 1%; CT± 5%
(see Figure 10)(see Figure 14)
Min
90
Typ
-2
12
15.5
19
8
11
3
Typ
100
7.1
3.7
Max
16
9
12
Max
110
Unit
mA
mA
mA
mA
V
V
V
Unit
KHz
V
V
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5 Page





VIPER100-E arduino
VIPer100-E
5 Operation Description
5 Operation Description
5.1 Current Mode Topology:
The current mode control method, like the one integrated in the VIPer100-E, uses two control
loops - an inner current control loop and an outer loop for voltage control. When the Power
MOSFET output transistor is on, the inductor current (primary side of the transformer) is
monitored with a SenseFET technique and converted into a voltage VS proportional to this
current. When VS reaches VCOMP (the amplified output voltage error) the power switch is
switched off. Thus, the outer voltage control loop defines the level at which the inner loop
regulates peak current through the power switch and the primary winding of the transformer.
Excellent open loop D.C. and dynamic line regulation is ensured due to the inherent input
voltage feedforward characteristic of the current mode control. This results in improved line
regulation, instantaneous correction to line changes, and better stability for the voltage
regulation loop.
Current mode topology also ensures good limitation in case there is a short circuit. During the
first phase the output current increases slowly following the dynamic of the regulation loop.
Then it reaches the maximum limitation current internally set and finally stops because the
power supply on VDD is no longer correct. For specific applications the maximum peak current
internally set can be overridden by externally limiting the voltage excursion on the COMP pin.
An integrated blanking filter inhibits the PWM comparator output for a short time after the
integrated Power MOSFET is switched on. This function prevents anomalous or premature
termination of the switching pulse in case there are current spikes caused by primary side
capacitance or secondary side rectifier reverse recovery time.
5.2 Stand-by Mode
Stand-by operation in nearly open load conditions automatically leads to a burst mode
operation allowing voltage regulation on the secondary side. The transition from normal
operation to burst mode operation happens for a power PSTBY given by :
Where:
PSTBY
=
1--
2
LP
I2
S
T
BYFS
W
LP is the primary inductance of the transformer. FSW is the normal switching frequency.
ISTBY is the minimum controllable current, corresponding to the minimum on time that the
device is able to provide in normal operation. This current can be computed as :
ISTBY
=
(---t--b---+-----t--d---)--V-----I--N--
Lp
tb + td is the sum of the blanking time and of the propagation time of the internal current sense
and comparator, and represents roughly the minimum on time of the device. Note: that PSTBY
may be affected by the efficiency of the converter at low load, and must include the power
drawn on the primary auxiliary voltage.
11/29

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