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PDF MAC4DLM Data sheet ( Hoja de datos )

Número de pieza MAC4DLM
Descripción Sensitive Gate Triacs Silicon Bidirectional Thyristors
Fabricantes ON Semiconductor 
Logotipo ON Semiconductor Logotipo



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MAC4DLM
Preferred Device
Sensitive Gate Triacs
Silicon Bidirectional Thyristors
Designed for high volume, low cost, industrial and consumer
applications such as motor control; process control; temperature, light
and speed control.
Features
Small Size Surface Mount DPAK Package
Passivated Die for Reliability and Uniformity
Four−Quadrant Triggering
Blocking Voltage to 600 V
On−State Current Rating of 4.0 Amperes RMS at 93°C
Low Level Triggering and Holding Characteristics
Epoxy Meets UL 94 V−0 @ 0.125 in
ESD Ratings: Human Body Model, 3B u 8000 V
Machine Model, C u 400 V
Pb−Free Packages are Available
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol Value
Peak Repetitive Off−State Voltage (Note 1)
(TJ = −40 to 110°C, Sine Wave,
50 to 60 Hz, Gate Open)
VDRM,
VRRM
600
Unit
V
On−State RMS Current
(Full Cycle Sine Wave, 60 Hz, TC = 93°C)
Peak Non-Repetitive Surge Current
(One Full Cycle, 60 Hz, TJ = 110°C)
Circuit Fusing Consideration (t = 8.3 msec)
IT(RMS)
ITSM
I2t
4.0 A
40 A
6.6 A2sec
Peak Gate Power
(Pulse Width 10 msec, TC = 93°C)
PGM 0.5 W
Average Gate Power
(t = 8.3 msec, TC = 93°C)
PG(AV)
0.1
W
Peak Gate Current
(Pulse Width 10 msec, TC = 93°C)
IGM 0.2 A
Peak Gate Voltage
(Pulse Width 10 msec, TC = 93°C)
VGM
5.0
V
Operating Junction Temperature Range
TJ −40 to 110 °C
Storage Temperature Range
Tstg −40 to 150 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. VDRM and VRRM for all types can be applied on a continuous basis. Blocking
voltages shall not be tested with a constant current source such that the
voltage ratings of the device are exceeded.
http://onsemi.com
TRIACS
4.0 AMPERES RMS
600 − 800 VOLTS
MT2
MT1
G
12
3
4
DPAK
CASE 369C
STYLE 6
MARKING
DIAGRAMS
YWW
AC
4DLMG
1
2
3
4
DPAK−3
CASE 369D
STYLE 6
YWW
AC
4DLMG
Y
WW
AC4DLM
G
= Year
= Work Week
= Device Code
= Pb−Free Package
PIN ASSIGNMENT
1 Main Terminal 1
2 Main Terminal 2
3 Gate
4 Main Terminal 2
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
Preferred devices are recommended choices for future use
and best overall value.
© Semiconductor Components Industries, LLC, 2005
November, 2005 − Rev. 3
1
Publication Order Number:
MAC4DLM/D

1 page




MAC4DLM pdf
MAC4DLM
5.0
4.0
3.0
MT2 NEGATIVE
2.0
MT2 POSITIVE
1.0
0
−40 −25 −10 5.0 20 35 50 65 80
TJ, JUNCTION TEMPERATURE (°C)
95 110
Figure 7. Typical Holding Current versus
Junction Temperature
12
10
8.0
Q2
6.0
4.0
Q4
2.0 Q1
Q3
0
−40 −25 −10 5.0 20 35 50 65 80
TJ, JUNCTION TEMPERATURE (°C)
95 110
Figure 8. Typical Latching Current versus
Junction Temperature
40
35
VD = 400 V
TJ = 110°C
30
25
20
15 MAC4DLM
10
5.0
100
1000
RGK, GATE−MT1 RESISTANCE (OHMS)
10 K
Figure 9. Minimum Exponential Static dv/dt
versus Gate−MT1 Resistance
10
VPK = 400 V
TJ = 110°C 100°C 90°C
1.0
tw
VDRM
1
f=
2 tw
(di/dt)c
=
6f ITM
1000
0.1
0 1.0 2.0 3.0 4.0 5.0 6.0
di/dt(c), RATE OF CHANGE OF COMMUTATING CURRENT (A/ms)
Figure 10. Critical Rate of Rise of
Commutating Voltage
200 VRMS
ADJUST FOR
ITM, 60 Hz VAC
TRIGGER
CHARGE
CHARGE
CONTROL
NON-POLAR
CL
LL
MEASURE
I
RS
1N4007
MT2
1N914 51 W
G
CS
MT1
ADJUST FOR +
di/dt(c)
200 V
Note: Component values are for verification of rated (di/dt)c. See AN1048 for additional information.
Figure 11. Simplified Test Circuit to Measure the Critical Rate of Rise of Commutating Current (di/dt)c
http://onsemi.com
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