PDF M366S6453CTS Data sheet ( Hoja de datos )

Número de pieza	M366S6453CTS
Descripción	PC133/PC100 Unbuffered DIMM
Fabricantes	Samsung semiconductor
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No Preview Available ! www.DataSheet4U.com M366S6453CTS PC133/PC100 Unbuffered DIMM M366S6453CTS SDRAM DIMM 64Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD GENERAL DESCRIPTION The Samsung M366S6453CTS is a 64M bit x 64 Synchronous Dynamic RAM high density memory module. The Samsung M366S6453CTS consists of sixteen CMOS 32M x 8 bit with 4banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The M366S6453CTS is a Dual In-line Memory Module and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. FEATURE • Performance range Part No. M366S6453CTS-L7C/C7C M366S6453CTS-L7A/C7A M366S6453CTS-L1H/C1H M366S6453CTS-L1L/C1L Max Freq. (Speed) 133MHz@CL=2/3 133MHz@CL=3/100MHz@CL=2 100MHz @ CL=2/3 100MHz @ CL=3 • Burst mode operation • Auto & self refresh capability (8192 Cycles/64ms) • LVTTL compatible inputs and outputs • Single 3.3V ± 0.3V power supply • MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) • All inputs are sampled at the positive going edge of the system clock • Serial presence detect with EEPROM • PCB : Height (1,375mil), double sided component PIN CONFIGURATIONS (Front side/back side) Pin Front Pin Front Pin Front Pin Back Pin Back Pin Back 1 VSS 29 DQM1 57 DQ18 85 VSS 113 DQM5 141 DQ50 2 DQ0 30 CS0 58 DQ19 86 DQ32 114 CS1 142 DQ51 3 DQ1 31 DU 59 VDD 87 DQ33 115 RAS 143 VDD 4 DQ2 32 VSS 60 DQ20 88 DQ34 116 VSS 144 DQ52 5 DQ3 33 A0 61 NC 89 DQ35 117 A1 145 NC 6 VDD 34 A2 62 VREF 90 VDD 118 A3 146 VREF 7 DQ4 35 A4 63 CKE1 91 DQ36 119 A5 147 NC 8 DQ5 36 A6 64 VSS 92 DQ37 120 A7 148 VSS 9 DQ6 37 A8 65 DQ21 93 DQ38 121 A9 149 DQ53 10 DQ7 38 A10/AP 66 DQ22 94 DQ39 122 BA0 150 DQ54 11 DQ8 39 BA1 67 DQ23 95 DQ40 123 A11 151 DQ55 12 VSS 40 VDD 68 VSS 96 VSS 124 VDD 152 VSS 13 DQ9 41 VDD 69 DQ24 97 DQ41 125 CLK1 153 DQ56 14 DQ10 42 CLK0 70 DQ25 98 DQ42 126 A12 154 DQ57 15 DQ11 43 VSS 71 DQ26 99 DQ43 127 VSS 155 DQ58 16 DQ12 44 DU 72 DQ27 100 DQ44 128 CKE0 156 DQ59 17 DQ13 45 CS2 73 VDD 101 DQ45 129 CS3 157 VDD 18 VDD 46 DQM2 74 DQ28 102 VDD 130 DQM6 158 DQ60 19 DQ14 47 DQM3 75 DQ29 103 DQ46 131 DQM7 159 DQ61 20 DQ15 48 DU 76 DQ30 104 DQ47 132 A13 160 DQ62 21 CB0 49 VDD 77 DQ31 105 CB4 133 VDD 161 DQ63 22 CB1 50 NC 78 VSS 106 CB5 134 NC 162 VSS 23 VSS 51 NC 79 CLK2 107 VSS 135 NC 163 CLK3 24 NC 52 CB2 80 NC 108 NC 136 CB6 164 NC 25 NC 53 CB3 81 WP 109 NC 137 CB7 165 SA0 26 VDD 54 VSS 82 SDA 110 VDD 138 VSS 166 SA1 27 WE 55 DQ16 83 SCL 111 CAS 139 DQ48 167 *SA2 28 DQM0 56 DQ17 84 VDD 112 DQM4 140 DQ49 168 VDD PIN NAMES Pin Name Function A0 ~ A12 Address input (Multiplexed) BA0 ~ BA1 Select bank DQ0 ~ DQ63 Data input/output CLK0 ~ CLK3 Clock input CKE0 ~ CKE1 Clock enable input CS0 ~ CS3 Chip select input RAS Row address strobe CAS Column address strobe WE Write enable DQM0 ~ 7 DQM VDD Power supply (3.3V) VSS Ground VREF Power supply for reference SDA Serial data I/O SCL Serial clock SA0 ~ 2 Address in EEPROM WP Write protection DU Don′t use NC No connection These pins are not used in this module. ** These pins should be NC in the system which does not support SPD. SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. REV. 0.0 Sept. 2001 1 page M366S6453CTS PC133/PC100 Unbuffered DIMM DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) Parameter Operating current (One bank active) Symbol Test Condition ICC1 Burst length = 1 tRC ≥ tRC(min) IO = 0 mA Version Unit Note -7C -7A -1H -1L 1040 960 960 960 mA 1 Precharge standby cur- rent in power-down mode Precharge standby cur- rent in non power-down mode ICC2P ICC2PS ICC2N CKE ≤ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tCC = ∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns ICC2NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 32 mA 32 320 mA 160 Active standby current in power-down mode Active standby current in non power-down mode (One bank active) ICC3P ICC3PS ICC3N CKE ≤ VIL(max), tCC = 10ns CKE & CLK ≤ VIL(max), tCC = ∞ CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns Input signals are changed one time during 20ns ICC3NS CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞ Input signals are stable 96 mA 96 480 mA 400 mA Operating current (Burst mode) Refresh current Self refresh current ICC4 ICC5 IO = 0 mA Page burst 4banks Activated. tCCD = 2CLKs tRC ≥ tRC(min) ICC6 CKE ≤ 0.2V 1120 1120 1040 1040 mA 1 2,000 1,840 1,760 1,760 mA 2 C 48 mA L 24 mA Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). REV. 0.0 Sept. 2001 5 Page M366S6453CTS PC133/PC100 Unbuffered DIMM SERIAL PRESENCE DETECT INFORMATION Byte # Function described Function Supported Hex value Note -7C -7A -1H -1L -7C -7A -1H -1L 35 Data signal input hold time 0.8ns 0.8ns 1ns 1ns 08h 08h 10h 10h 36~61 Superset information (maybe used in future) - 00h 62 SPD data revision code Current release Intel spd 1.2B/A 12h 63 Checksum for bytes 0 ~ 62 - 92h D3h 3Ah 6Ah 64 Manufacturer JEDEC ID code Samsung CEh 65~71 ...... Manufacturer JEDEC ID code Samsung 00h 72 Manufacturing location Onyang Korea 01h 73 Manufacturer part # (Memory module) M 4Dh 74 Manufacturer part # (DIMM configuration) 3 33h 75 Manufacturer part # (Data bits) Blank 20h 76 ...... Manufacturer part # (Data bits) 6 36h 77 ...... Manufacturer part # (Data bits) 6 36h 78 Manufacturer part # (Mode & operating voltage) S 53h 79 Manufacturer part # (Module depth) 6 36h 80 ...... Manufacturer part # (Module depth) 4 34h 81 Manufacturer part # (Refresh, # of banks in Comp. & inter- 5 35h 82 Manufacturer part # (Composition component) 3 33h 83 Manufacturer part # (Component revision) C 43h 84 Manufacturer part # (Package type) T 54h 85 Manufacturer part # (PCB revision & type) S 53h 86 Manufacturer part # (Hyphen) " - " 2Dh 87 Manufacturer part # (Power) L/C 4Ch / 43h 88 Manufacturer part # (Minimum cycle time) 7 7 1 1 37h 37h 31h 31h 89 Manufacturer part # (Minimum cycle time) C A H L 43h 41h 48h 4Ch 90 Manufacturer part # (TBD) Blank 20h 91 Manufacturer revision code (For PCB) S 53h 92 ...... Manufacturer revision code (For component) C-die (4th Gen.) 43h 93 Manufacturing date (Year) - -3 94 Manufacturing date (Week) - -3 95~98 Assembly serial # - -4 99~12 Manufacturer specific data (may be used in future) Undefined -5 126 System frequency for 100MHz 100MHz 64h 127 Intel Specification details Detailed 100MHz Information FFh FFh FFh FDh 128+ Unused storage locations Undefined -5 Note : 1. The bank select address is excluded in counting the total # of addresses. 2. This value is based on the component specification. 3. These bytes are programmed by code of Date Week & Date Year with BCD format. 4. These bytes are programmed by Samsung ′s own Assembly Serial # system. All modules may have different unique serial #. 5. These bytes are Undefined and can be used for Samsung ′s own purpose. REV. 0.0 Sept. 2001 11 Page

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