DataSheet.es    


PDF FIN3384 Data sheet ( Hoja de datos )

Número de pieza FIN3384
Descripción (FIN3383 - FIN3386) Low Voltage 28-Bit Flat Panel Display Link Serializers/Deserializers
Fabricantes Fairchild Semiconductor 
Logotipo Fairchild Semiconductor Logotipo



Hay una vista previa y un enlace de descarga de FIN3384 (archivo pdf) en la parte inferior de esta página.


Total 18 Páginas

No Preview Available ! FIN3384 Hoja de datos, Descripción, Manual

www.DataSheet4U.com
October 2003
Revised April 2005
FIN3385 FIN3383
FIN3384 FIN3386
Low Voltage 28-Bit Flat Panel Display Link
Serializers/Deserializers
General Description
The FIN3385 and FIN3383 transform 28 bit wide parallel
LVTTL (Low Voltage TTL) data into 4 serial LVDS (Low
Voltage Differential Signaling) data streams. A phase-
locked transmit clock is transmitted in parallel with the data
stream over a separate LVDS link. Every cycle of transmit
clock 28 bits of input LVTTL data are sampled and trans-
mitted.
The FIN3386 and FIN3384 receive and convert the 4/3
serial LVDS data streams back into 28/21 bits of LVTTL
data. Refer to Table 1 for a matrix summary of the Serializ-
ers and Deserializers available. For the FIN3385, at a
transmit clock frequency of 85MHz, 28 bits of LVTTL data
are transmitted at a rate of 595Mbps per LVDS channel.
These chipsets are an ideal solution to solve EMI and cable
size problems associated with wide and high-speed TTL
interfaces.
Features
s Low power consumption
s 20 MHz to 85 MHz shift clock support
s r1V common-mode range around 1.2V
s Narrow bus reduces cable size and cost
s High throughput (up to 2.38 Gbps throughput)
s Internal PLL with no external component
s Compatible with TIA/EIA-644 specification
s Devices are offered 56-lead TSSOP packages
Ordering Code:
Order Number Package Number
Package Description
FIN3383MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN3384MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN3385MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN3386MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Part
FIN3385
FIN3383
FIN3386
FIN3384
TABLE 1. Display Panel Link Serializers/Deserializers Chip Matrix
CLK Frequency
85
66
85
66
LVTTL IN
28
28
LVDS OUT
4
4
LVDS IN LVTTL OUT
4 28
4 28
Package
56 TSSOP
56 TSSOP
56 TSSOP
56 TSSOP
© 2005 Fairchild Semiconductor Corporation DS500864
www.fairchildsemi.com

1 page




FIN3384 pdf
Transmitter and Receiver Power-Up/Power-Down Operation Truth Table
The outputs of the transmitter remain in the High-Impedance state until the power supply reaches 2V. The following table
shows the operation of the transmitter during power-up and power-down and operation of the PwrDn pin.
Transmitter
Receiver
H HIGH Logic Level
L LOW Logic Level
P Last Valid State
X Don’t Care
Z High-Impedance
VCC
TxIn
TxOut
TxCLKIn
TxCLKOutr
PwrDn
RxInr
RxOut
RxCLKInr
RxCLKOut
PwrDn
VCC
2V
X
Z
X
Z
L
X
Z
X
Z
L
2V
PwrDn
!2V
X
Z
X
Z
L
PwrDn
X
L
X
(Note 5)
L
2V
Normal
!2V
Active
Active
Active
Active
H
Active
L/H
Active
Active
H
2V
!2V
Active
X
H/L/Z
(Note 3)
H
Active
P
(Note 4)
(Note 5)
H
2V
!2V
H
(Note 4)
H
Active
(Note 5)
H
2V
!2V
H
(Note 4)
P
(Note 4)
(Note 5)
H
2V
Note 3: If the transmitter is powered up and PwrDn is inactive HIGH and the clock input goes to any state LOW, HIGH, or Z then the internal PLL will go to a
known low frequency and stay until the clock starts normal operation again.
Note 4: If the input is terminated and un-driven (Z) or shorted or open. (fail safe condition)
Note 5: For PwrDn or fail safe condition the RxCLKOut pin will go LOW for Panel Link devices and HIGH for Channel Link devices.
Note 6: Shorted here means (r inputs are shorted to each other, or r inputs are shorted to each other and Ground or VCC, or either r inputs are shorted to
Ground or VCC) with no other Current/Voltage sources (noise) applied. If the VID is still in the valid range (greater than 100mV) and VCM is in the valid range
(0V to 2.4V) then the input signal is still recognized and the part will respond normally.
5 www.fairchildsemi.com

5 Page





FIN3384 arduino
AC Loading and Waveforms
Note: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVTTL/CMOS I/O. Depending on the valid strobe edge of
transmitter, the TxCLKIn can be either rising or falling edge data strobe.
FIGURE 3. Worst CaseTest Pattern
FIGURE 4. Transmitter LVDS Output Load and Transition Times
FIGURE 5. Transmitter Setup/Hold and HIGH/LOW Times (Rising Edge Strobe)
FIGURE 6. Transmitter Input Clock Transition Time
11 www.fairchildsemi.com

11 Page







PáginasTotal 18 Páginas
PDF Descargar[ Datasheet FIN3384.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
FIN3383(FIN3383 - FIN3386) Low Voltage 28-Bit Flat Panel Display Link Serializers/DeserializersFairchild Semiconductor
Fairchild Semiconductor
FIN3384(FIN3383 - FIN3386) Low Voltage 28-Bit Flat Panel Display Link Serializers/DeserializersFairchild Semiconductor
Fairchild Semiconductor
FIN3385(FIN3383 - FIN3386) Low Voltage 28-Bit Flat Panel Display Link Serializers/DeserializersFairchild Semiconductor
Fairchild Semiconductor
FIN3386(FIN3383 - FIN3386) Low Voltage 28-Bit Flat Panel Display Link Serializers/DeserializersFairchild Semiconductor
Fairchild Semiconductor

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar