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PDF CDP1833 Data sheet ( Hoja de datos )

Número de pieza CDP1833
Descripción CMOS 7-Bit Latch and Decoder Memory Interface
Fabricantes Intersil 
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No Preview Available ! CDP1833 Hoja de datos, Descripción, Manual

March 1997
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CDP1883,
CDP1883C
CMOS 7-Bit Latch
and Decoder Memory Interfaces
Features
• Performs Memory Address Latch and Decoder Func-
tions Multiplexed or Non-Multiplexed
• Interfaces Directly with the CDP1800-Series Micropro-
cessors
• Allows Decoding for Systems Up to 32K Bytes
Ordering Information
5V 10V
CDP1883CE CDP1883E
TEMP.
RANGE
-40oC to
+85oC
PKG.
PACKAGE NO.
PDIP
E20.3
Description
The CDP1883 is a CMOS 7-bit memory latch and decoder
circuit intended for use in CDP1800-series microprocessor
systems. It can serve as a direct interface between the multi-
plexed address bus of this system and up to four 8K x 8-bit
memories to implement a 32K-byte memory system. With
four 4K x 8-bit memories, a 16K-byte system can be
decoded.
The device is also compatible with non-multiplexed address
bus microprocessors. By connecting the clock input to VDD,
the latches are in the data-following mode and the decoded
outputs can be used in general-purpose memory-system
applications.
The CDP1833 is compatible with CDP1800-series micropro-
cessors operating at maximum clock frequency.
The CDP1883 and CDP1883C are functionally identical.
They differ in that the CDP1883 has a recommended operat-
ing voltage range of 4V to 10.5V and the C version has a
recommended operating voltage range of 4V to 6.5V.
The CDP1883 and CDP1883C are supplied in 20 lead dual-
in-line plastic packages (E Suffix).
Pinout
CDP1883, CDP1883C
(PDIP)
TOP VIEW
CLOCK 1
MA0 2
MA1 3
MA2 4
MA3 5
MA4 6
MA5 7
MA6 8
CE 9
VSS 10
20 VDD
19 A8
18 A9
17 A10
16 A11
15 A12
14 CS0
13 CS1
12 CS2
11 CS3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
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File Number 1507.2

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CDP1833 pdf
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CDP1883, CDP1883C
Dynamic Electrical Specifications TA = -40oC to +85oC, VDD ± 5%, tR, tF = 20ns, VIH = 0.7 VDD, VIL = 0.3 VDD, CL = 100pF.
See Figure 1 (Continued)
CDP1883
CDP1883C
PARAMETER
VDD
(NOTE 1) (NOTE 2)
(NOTE 1) (NOTE 2)
(V) MIN TYP
MAX MIN TYP
MAX UNITS
CLOCK to Address
tCLA 5 - 100 175 - 100 175 ns
10 -
65 125 -
-
- ns
Memory Address to Chip Select
tMACS
5
- 100 175 - 100 175 ns
10 -
75 125 -
-
- ns
Memory Address to Address
tMAA 5 - 80 125 - 80 125 ns
10 - 40 60 -
-
- ns
NOTES:
1. Typical values are for TA = 25oC.
2. Maximum limits of minimum characteristics are the values above which all devices function.
CE
CS0, CS1, CS2, CS3
VALID CHIP ENABLE
tCECS
tCECS
(A) CHIP ENABLE TO CHIP SELECT PROPAGATION DELAY
MA0 - MA5
tMACL
CLOCK
tCLCL
CS0, CS1, CS2, CS3
tCLA
A8 - A12
tCLMA
tCLCS
tMACS
(B) MEMORY ADDRESS SETUP AND HOLD TIME
tMAA
tMAA
tMACS
FIGURE 1. CDP1883 TIMING WAVEFORMS
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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