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PDF M25PE40 Data sheet ( Hoja de datos )
| Número de pieza | M25PE40 | |
| Descripción | Page-Erasable Serial Flash memory | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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M25PE40
4 Mbit, low voltage, Page-Erasable Serial Flash memory with
byte alterability, 50 MHz SPI bus, standard pinout
Features
■ SPI bus compatible serial interface
■ 4 Mbit Page-Erasable Flash memory
■ Page size: 256 bytes
– Page Write in 11 ms (typical)
– Page Program in 0.8 ms (typical)
– Page Erase in 10 ms (typical)
■ SubSector Erase (4 Kbytes)
■ Sector Erase (64 Kbytes)
■ Bulk Erase (4 Mbits)
■ 2.7 V to 3.6 V single supply voltage
■ 50 MHz clock rate (maximum)
■ Deep Power-down mode 1 µA (typical)
■ Electronic Signature
– JEDEC standard two-byte signature
(8013h)
■ Software Write Protection on a 64 Kbyte sector
basis
■ Hardware Write Protection of the memory area
selected using the BP0, BP1 and BP2 bits
■ More than 100 000 Write cycles
■ More than 20 year data retention
■ Packages
– ECOPACK® (RoHS compliant)
VFQFPN8 (MP)
6 × 5 mm (MLP8)
SO8W (MW) 208 mils width
SO8N (MN) 150 mils width
January 2007
Rev 7
1/59
www.st.com
1
1 page  
M25PE40
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Logic diagram - previous T7X process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic diagram - new T9HX process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VFQFPN and SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Identification (RDID) instruction sequence and Data-out sequence . . . . . . . . . . . . . 23
Read Status Register (RDSR) instruction sequence and Data-out sequence . . . . . . . . . . 25
Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Read Data Bytes (READ) instruction sequence and Data-out sequence . . . . . . . . . . . . . . 28
Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
and Data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Read Lock Register (RDLR) instruction sequence and data-out Sequence. . . . . . . . . . . . 30
Page Write (PW) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Write to Lock Register (WRLR) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Page Erase (PE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
SubSector Erase (SSE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Sector Erase (SE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Release from Deep Power-down (RDP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 41
Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Top Sector Lock (T7X process) or Write Protect (T9HX process) setup and hold
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
VFQFPN8 (MLP8) 8-lead Very thin Fine Pitch Quad Flat Package No lead
6 × 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
SO8N – 8 lead Plastic Small Outline, 150 mils body width, package outline . . . . . . . . . . . 55
SO8W – 8 lead Plastic Small Outline, 208 mils body width, package outline. . . . . . . . . . . 56
5/60
5 Page 
M25PE40
SPI modes
Example: Cp = 50 pF, that is R*Cp = 5 µs <=> the application must ensure that the Bus
Master never leaves the SPI bus in the high impedance state for a time period shorter than
5 µs.
Figure 5. SPI modes supported
CPOL CPHA
00
C
11
C
D MSB
Q MSB
AI01438B
11/60
11 Page | ||
| Páginas | Total 60 Páginas | |
| PDF Descargar | [ Datasheet M25PE40.PDF ] | |
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