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PDF KM44C16000B Data sheet ( Hoja de datos )

Número de pieza KM44C16000B
Descripción (KM44C16000B / KM44C16100B) 16M x 4bit CMOS Dynamic RAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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KM44C16000B, KM44C16100B
CMOS DRAM
16M x 4bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
This is a family of 16,777,216 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time(-45, -5 or -6), package type(SOJ or TSOP-II) are optional fea-
tures of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. This 16Mx4 Fast
Page Mode DRAM family is fabricated using Samsungs advanced CMOS process to realize high band-width, low power consumption
and high reliability.
FEATURES
• Part Identification
- KM44C16000B(5.0V, 8K Ref.)
- KM44C16100B(5.0V, 4K Ref.)
Active Power Dissipation
Speed
-45
-5
-6
8K
550
495
440
Unit : mW
4K
715
660
605
Refresh Cycles
Part
NO.
KM44C16000B*
KM44C16100B
Refresh
cycle
8K
4K
Refresh time
Normal
64ms
* Access mode & RAS only refresh mode
: 8K cycle/64ms
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms
Performance Range
Speed tRAC
tCAC
-45 45ns 12ns
-5 50ns 13ns
-6 60ns 15ns
tRC
80ns
90ns
110ns
tPC
31ns
35ns
40ns
• Fast Page Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Fast parallel test mode capability
• TTL(5.0V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• +5.0V±10% power supply
FUNCTIONAL BLOCK DIAGRAM
RAS
CAS
W
Control
Clocks
VBB Generator
Vcc
Vss
Refresh Timer
Refresh Control
Refresh Counter
A0~A12
(A0~A11)*1
A0~A10
(A0~A11)*1
Row Address Buffer
Col. Address Buffer
Note) *1 : 4K Refresh
Row Decoder
Memory Array
16,777,216 x 4
Cells
Column Decoder
Data in
Buffer
Data out
Buffer
DQ0
to
DQ3
OE
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.

1 page




KM44C16000B pdf
KM44C16000B, KM44C16100B
CAPACITANCE (TA=25°C, VCC=5.0V, f=1MHz)
Parameter
Symbol
Input capacitance [A0 ~ A12]
CIN1
Input capacitance [RAS, CAS, W, OE]
CIN2
Output capacitance [DQ0 - DQ3]
CDQ
Min
-
-
-
CMOS DRAM
Max Units
5 pF
7 pF
7 pF
AC CHARACTERISTICS (0°CTA70°C, See note 1,2)
Test condition : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V
Parameter
Symbol
-45
Min Max
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay
Transition time (rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
tRC
tRWC
tRAC
tCAC
tAA
tCLZ
tOFF
tT
tRP
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
80
115
45
12
23
0
0 13
1 50
25
45 10K
12
45
12 10K
18 33
13 22
5
0
8
0
8
23
0
0
0
8
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data set-up time
Data hold time
tWP
tRWL
tCWL
tDS
tDH
8
13
12
0
10
-5
Min Max
90
133
50
13
25
0
0 13
1 50
30
50 10K
13
50
13 10K
20 37
15 25
5
0
10
0
10
25
0
0
0
10
10
15
13
0
10
-6
Min Max
110
153
60
15
30
0
0 13
1 50
40
60 10K
15
60
15 10K
20 45
15 30
5
0
10
0
10
30
0
0
0
10
10
15
15
0
10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
3,4,10
3,4,5
3,10
3
6
2
4
10
8
8
9
9

5 Page





KM44C16000B arduino
KM44C16000B, KM44C16100B
WRITE CYCLE ( OE CONTROLLED WRITE )
NOTE : DOUT = OPEN
VIH -
RAS
VIL -
VIH -
CAS
VIL -
VIH -
A
VIL -
VIH -
W
VIL -
VIH -
OE
VIL -
DQ0 ~ DQ3(7)
VIH -
VIL -
tRAS
tRC
tCRP
tRCD
tASR
tRAD
tRAH
tASC
ROW
ADDRESS
tCSH
tRSH
tCAS
tCAH
COLUMN
ADDRESS
tRAL
tCWL
tRWL
tWP
tOED
tOEH
tDS tDH
DATA-IN
CMOS DRAM
tRP
tCRP
Dont care
Undefined

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