|
|
PDF XC3S250E Data sheet ( Hoja de datos )
| Número de pieza | XC3S250E | |
| Descripción | (XC3Sxx00E) Spartan-3E FPGA Family | |
| Fabricantes | Xilinx | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de XC3S250E (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
0
R Spartan-3E FPGA Family:
Complete Data Sheet
DS312 March 21, 2005
00
Module 1:
Introduction and Ordering Information
DS312-1 (v1.1) March 21, 2005
6 pages
• Introduction
• Features
• Architectural Overview
• Package Marking
• Ordering Information
Module 2:
Functional Description
DS312-2 (v1.1) March 21, 2005
96 pages
• Input/Output Blocks (IOBs)
- Overview
- SelectIO™ Signal Standards
• Configurable Logic Block (CLB)
• Block RAM
• Dedicated Multipliers
• Digital Clock Manager (DCM)
• Clock Network
• Configuration
• Powering Spartan-3E FPGAs
Module 3:
DC and Switching Characteristics
DS312-3 (v1.0) March 1, 2005
18 pages
• DC Electrical Characteristics
- Absolute Maximum Ratings
- Supply Voltage Specifications
- Recommended Operating Conditions
- DC Characteristics
• Switching Characteristics
- DCM Timing
- Configuration and JTAG Timing
Module 4:
Pinout Descriptions
DS312-4 (v1.1) March 21, 2005
72 pages
• Pin Descriptions
• Package Overview
• Pinout Tables
• Footprint Diagrams
IMPORTANT NOTE: The Spartan™-3E FPGA data sheet is created and published in separate modules. This complete
version is provided for easy downloading and searching of the complete document. Page, figure, and table numbers begin
at 1 for each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" for easy
navigation in this volume.
© 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.
All other trademarks are the property of their respective owners.
DS312 March 21, 2005
www.xilinx.com
1
1 page  
Introduction and Ordering Information
R
Package Marking
Figure 2 provides a top marking example for Spartan-3E
FPGAs in the quad-flat packages. Figure 3 shows the top
marking for Spartan-3E FPGAs in BGA packages except
the 132-ball chip-scale package (CP132 and CPG132). The
markings for the BGA packages are nearly identical to those
for the quad-flat packages, except that the marking is
rotated with respect to the ball A1 indicator. Figure 4 shows
the top marking for Spartan-3E FPGAs in the CP132 and
CPG132 packages.
Use the seven digits of the Lot Code to access additional
information for a specific device using the Xilinx web-based
Genealogy Viewer.
Mask Revision Code
Device Type
Package
Speed Grade
Temperature Range
R
SPARTAN R
XC3S250ETM
PQ208AGQ0525
D1234567A
4C
Fabrication Code
Process Technology
Date Code
Lot Code
Pin P1
DS312-1_06_032105
Figure 2: Spartan-3E QFP Example Package Marking
BGA Ball A1
Device Type
Package
Speed Grade
Temperature Range
R
SPARTAN R
XC3S250ETM
FT256AGQ0525
D1234567A
4C
Mask Revision Code
Fabrication Code
Process Code
Date Code
Lot Code
DS312-1_02_032105
Figure 3: Spartan-3E BGA Example Package Marking
Ball A1
3S250E
Device Type
Lot Code
F1234567-0525
Date Code
PHILIPPINES
Temperature Range
Package
C5 = CP132
C5AGQ 4C
C6 = CPG132
Speed Grade
Process Code
Mask Revision Code
Fabrication Code
DS312-1_05_032105
Figure 4: Spartan-3E CP132 and CPG132 Example Package Marking
4
www.xilinx.com
DS312-1 (v1.1) March 21, 2005
Advance Product Specification
5 Page 
Functional Description
R
Storage Element Functions
There are three pairs of storage elements in each IOB, one
pair for each of the three paths. It is possible to configure
each of these storage elements as an edge-triggered
D-type flip-flop (FD) or a level-sensitive latch (LD).
The storage-element pair on either the Output path or the
Three-State path can be used together with a special multi-
plexer to produce Double-Data-Rate (DDR) transmission.
This is accomplished by taking data synchronized to the
clock signal’s rising edge and converting it to bits syn-
chronized on both the rising and the falling edge. The com-
bination of two registers and a multiplexer is referred to as a
Double-Data-Rate D-type flip-flop (ODDR2).
Table 1 describes the signal paths associated with the stor-
age element.
Table 1: Storage Element Signal Description
Storage
Element
Signal
Description
Function
D Data input
Data at this input is stored on the active edge of CK and enabled by CE. For latch
operation when the input is enabled, data passes directly to the output Q.
Q Data output
The data on this output reflects the state of the storage element. For operation as a latch
in transparent mode, Q mirrors the data at D.
CK Clock input
Data is loaded into the storage element on this input’s active edge with CE asserted.
CE Clock Enable input When asserted, this input enables CK. If not connected, CE defaults to the asserted
state.
SR
Set/Reset input
This input forces the storage element into the state specified by the SRHIGH/SRLOW
attributes. The SYNC/ASYNC attribute setting determines if the SR input is
synchronized to the clock or not. If both SR and REV are active at the same time, the
storage element gets a value of 0.
REV
Reverse input
This input is used together with SR. It forces the storage element into the state opposite
from what SR does. The SYNC/ASYNC attribute setting determines whether the REV
input is synchronized to the clock or not. If both SR and REV are active at the same time,
the storage element gets a value of 0.
As shown in Figure 1, the upper registers in both the output
and three-state paths share a common clock. The OTCLK1
clock signal drives the CK clock inputs of the upper registers
on the output and three-state paths. Similarly, OTCLK2
drives the CK inputs for the lower registers on the output
and three-state paths. The upper and lower registers on the
input path have independent clock lines: ICLK1 and ICLK2.
The OCE enable line controls the CE inputs of the upper
and lower registers on the output path. Similarly, TCE con-
trols the CE inputs for the register pair on the three-state
path and ICE does the same for the register pair on the
input path.
The Set/Reset (SR) line entering the IOB controls all six
registers, as is the Reverse (REV) line.
In addition to the signal polarity controls described in IOB
Overview, each storage element additionally supports the
controls described in Table 2.
Table 2: Storage Element Options
Option Switch
Function
Specificity
FF/Latch
Chooses between an edge-triggered flip-flop Independent for each storage element
or a level-sensitive latch
SYNC/ASYNC
Determines whether the SR set/reset control is Independent for each storage element
synchronous or asynchronous
4
www.xilinx.com
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet XC3S250E.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| XC3S250E | (XC3Sxx00E) Spartan-3E FPGA Family | Xilinx |
| XC3S250E | Spartan-3 Generation FPGA User Guide | Xilinx |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |