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PDF DS16EV5110 Data sheet ( Hoja de datos )
| Número de pieza | DS16EV5110 | |
| Descripción | Video Equalizer | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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PRELIMINARY
March 2007
DS16EV5110
Video Equalizer for DVI, HDMI, and CAT5 Cables
General Description
The DS16EV5110 is a 1.65 Gbps multi-channel equalizer op-
timized for video cable extension applications. It contains
three transition-minimized differential signaling (TMDS) data
channels and one clock channel as commonly found in DVI
and HDMI cables. It provides compensation for skin-effect
losses, a common phenomenon when transmitting video on
commercially available high definition video cables.
The inputs and outputs are fully compliant with DVI 1.0 and
HDMI 1.2a requirements and features programmable levels
of input equalization, providing optimal signal boost and re-
ducing inter-symbol interference. The device supports DC-
coupled data paths providing a wider input common-mode
voltage range and eliminating the need for external coupling
capacitors, reducing solution size and cost.
The clock channel is optimized for clock rates of up to 165
MHz and features a signal detect circuit. The loss of signal
threshold is adjustable through a Serial Management Bus
(SMBus) interface to maximize noise immunity.
The DS16EV5110 also provides support for system power
management via output enable controls. Other controls are
provided via the SMBus enabling customization and opti-
mization for specific applications requirements. These include
programmable features such as output amplitude and boost
control as well as system level diagnostics.
Features
■ 8 levels of equalization settable by 3 pins or through the
SMBus interface
■ DC-Coupled inputs and outputs
■ Optimized for operation from 250 Mbps to 1.65 Gbps in
support of 480 I/P, 720 I/P, 1080 I/P or UXGA Resolutions
■ Two DS16EV5110 devices support DVI/HDMI Dual Link
■ DVI 1.0 and HDMI 1.2a Compliant TMDS Interface
■ Clock channel signal detect (LOS)
■ Enable for power savings standby mode
■ Serial Management Bus (SMBus) provides control of
boost, output amplitude, enable, and clock channel signal
detect threshold
■ Low power consumption: 530mW typical, 240mW standby
■ 0.13 UI total jitter at 1.65 Gbps including cable
■ Single 3.3V power supply
■ Small 7mm x 7mm, 48-pin leadless LLP package
■ -40°C to +85°C operating temperature range
■ Extends TMDS cable reach to:
1. > 40 meters over 24 AWG DVI Cable
2. > 20 meters over 28 AWG DVI Cable
3. > 20 meters over Cat5/Cat5e/Cat6 cables
4. Supports up to 20 meters at 2.25 Gbps over 28 AWG
HDMI cables
Applications
■ DVI/HDMI Cable Extenders / Switchers
■ Digital Routers and Switches
■ Projectors
■ High Definition Displays
Typical Application
© 2007 National Semiconductor Corporation 202162
20216224
www.national.com
1 page  
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VDD)
CMOS Input Voltage
CMOS Output Voltage
CML Input/Output Voltage
Junction Temperature
Storage Temperature
Lead Temp. (Soldering, 5 sec.)
−0.3V to +4V
−0.3V to +5.5V
-0.3V to (VDD + 0.3V)
-0.3V to (VDD + 0.3V)
+150°C
−65°C to +150°C
+260°C
ESD Rating
HBM, 1.5 kΩ, 100 pF
Thermal Resistance
θJA, No Airflow
>8 kV
30°C/W
Recommended Operating
Conditions (Notes 2, 3)
Supply Voltage
(VDD to GND)
Ambient Temperature
Min Typ
3.0 3.3
−40 25
Max Units
3.6 V
85 °C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless other specified. (Notes 2, 3)
Symbol
Parameter
Conditions
Min Typ
POWER
P
Power Supply Consumption
Device Enabled, VDD
530
EN = Low, Power Down Mode,
VDD
N Supply Noise Tolerance (Note 4) 50 Hz – 100 Hz
100 Hz – 10 MHz
10 MHz – 825 MHz
100
40
10
CML INPUTS
VIN Input Voltage Swing
Measured differentially at TPA
(Figure 1)
800
VICMDC
Input Common-Mode Voltage
DC-Coupled Requirement
Measured at TPB (Figure 1)
VDD-0.6
RLI
Differential Input Return Loss
100 MHz– 825MHz, with fixture's
effect de-embedded
10
RIN Input Resistance
CML OUTPUTS
IN+ to VDD and IN− to VDD
45 50
VO Output Voltage Swing
Measured differentially with OUT+
and OUT− terminated by 50Ω to
VDD
800
VOCM
tR, tF
Output common-mode Voltage
Transition Time
Measured Single-endedly
20% to 80% of differential output
voltage, measured with 1" from
output pins.
VDD-0.6
75
tCCSK
Inter Pair Channel-to-Channel
Skew (all 4 Channels)
Difference in 50% crossing
between channels
50
tDSK Intra Pair Skew
tPPSK
Part-to-Part Skew
OUTPUT JITTER
TBD
TJ1 Total Jitter at 1.65 Gbps 22dB Skin Effect Loss Data Paths
EQ Setting 0x04 PRBS7
(Note 5)
(Note 6)
(Note 7)
TJ2 Total Jitter at 165 MHz
22dB Skin Effect Loss Clock Paths
Clock Pattern
(Note 5)
(Note 6)
(Note 7)
Max
730
TBD
Units
mW
mW
mVP-P
mVP-P
mVP-P
1200
VDD-0.4
mVP-P
V
dB
55 Ω
1200
VDD-0.4
240
mVP-P
V
ps
pS
pS
200 pS
0.2 UIP-P
0.165
UIP-P
5 www.national.com
5 Page 
CLOCK CHANNEL SIGNAL DETECT
The DS16EV5110 features a signal detect circuit on the clock
channel. The status of the clock signal can be determined by
either reading the Signal Detect bit (SD) in the SMBus regis-
ters (see Table 1) or by the state of the SD pin. A logical high
indicates the presence of a signal that has exceeded a spec-
ified maximum threshold value (called SD_ON). A logical low
means that the clock signal has fallen below a minimum
threshold value (called SD_OFF). These values are pro-
grammed via the SMBus (Table 1). If not programmed via the
SMBus, the minimum and maximum thresholds take on the
default values for the minimum and maximum values as indi-
cated in Table 4. The Signal Detect threshold values can be
changed through the SMBus.
TABLE 4. Clock Channel Signal Detect Threshold Values
Bit 1 Bit 0 Minimum Threshold Maximum Threshold
— Register 06 (mV) — Register 05 (mV)
00
30 (Default)
100 (Default)
01
10
60
10
60
160
11
40
120
OUTPUT LEVEL CONTROL
The output amplitude of the TDMS drivers for both the data
channels and the clock channel can be controlled via the SM-
Bus (see Table 1). The default output level is TBD mV p-p.
The following Table presents the output level values support-
ed:
TABLE 5. Output Level Control Settings
Bit 3
Bit 2
Output Level (mV)
00
TBD
01
TBD
10
TBD
11
TBD
AUTOMATIC ENABLE FEATURE
It may be desired for the DS16EV5110 to be configured to
automatically enter STANDBY mode if no clock signal is
present. This is implemented by connecting the Signal Detect
(SD) pin to the external (CMOS) Enable (EN) pin. In order for
this option to function properly, the FEB pin must be either
tied high or not connected (the FEB pin is internally pulled
high by default). If the clock signal applied to the clock channel
input swings above the maximum level specified in the thresh-
old register via the SMBus, then the SD pin is asserted high.
If the SD pin is connected to the EN pin, this will enable the
equalizer, limiting amplifier, and output buffer on the data
channels as well as the limiting amplifier and output buffer on
the clock channel (provided that the FEB pin is high); thus the
DS16EV5110 will automatically enter the ACTIVE state. If the
clock signal present falls below the minimum level specified
in the threshold register, then the SD pin will be asserted low,
causing the aforementioned blocks to be placed in the
STANDBY state.
Application Information
The DS16EV5110 is used to recondition DVI/HDMI video sig-
nals or differential signals with similar characteristics after
signal loss and degradation due to transmission through a
length of shielded or unshielded cable.
FIGURE 4. DS16EV5110 Typical Use
20216239
DVI 1.0 ANDHDMI V1.2A APPLICATIONS
A single DS16EV5110 can be used to implement cable ex-
tension solutions with various resolutions and screen refresh
rates. The range of digital serial rates supported is between
250 Mbps and 1.65 Gbps. For applications requiring ultra-
high resolution for DVI applications (e.g., QXGA and WQX-
GA), a “dual link” TMDS interface is required. This is easily
configured by using two DS16EV5110 devices as shown in
Figure 5.
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| PDF Descargar | [ Datasheet DS16EV5110.PDF ] | |
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