DataSheet.es    


PDF LAN9218 Data sheet ( Hoja de datos )

Número de pieza LAN9218
Descripción High-Performance Single- Chip 10/100 Ethernet Controller
Fabricantes SMSC Corporation 
Logotipo SMSC Corporation Logotipo



Hay una vista previa y un enlace de descarga de LAN9218 (archivo pdf) en la parte inferior de esta página.


Total 70 Páginas

No Preview Available ! LAN9218 Hoja de datos, Descripción, Manual

www.DataSheet4U.com
LAN9218
High-Performance Single-
Chip 10/100 Ethernet
Controller with HP Auto-MDIX
PRODUCT FEATURES
Datasheet
Highlights
„ Optimized for the highest performance applications
„ Efficient architecture with low CPU overhead
„ Easily interfaces to most 32-bit and 16-bit embedded
CPU’s
„ Integrated PHY with HP Auto-MDIX
„ Supports audio & video streaming over Ethernet:
multiple high-definition (HD) MPEG2 streams
„ Compatible with other members of LAN9218 family
Target Applications
„ Video distribution systems, multi-room PVR
„ Cable, satellite, and IP set-top boxes
„ Digital video recorders and DVD recorder/players
„ High definition televisions
„ Digital media clients/servers and home gateways
„ Video-over IP Solutions, IP PBX & video phones
„ Wireless routers & access points
„ High-end audio distribution systems
Key Benefits
„ Non-PCI Ethernet controller for the highest
performance applications
— Highest performing non-PCI Ethernet controller
— 32-bit interface with fast bus cycle times
— Burst-mode read support
„ Eliminates dropped packets
— Internal buffer memory can store over 200 packets
— Automatic PAUSE and back-pressure flow control
„ Minimizes CPU overhead
— Supports Slave-DMA
— Interrupt Pin with Programmable Hold-off timer
„ Reduces system cost and increases design flexibility
„ SRAM-like interface easily interfaces to most
embedded CPU’s or SoC’s
„ Reduced Power Modes
— Numerous power management modes
— Wake on LAN*
— Magic packet wakeup*
— Wakeup indicator event signal
— Link Status Change
„ Single chip Ethernet controller
— Fully compliant with IEEE 802.3/802.3u standards
— Integrated Ethernet MAC and PHY
— 10BASE-T and 100BASE-TX support
— Full- and Half-duplex support
— Full-duplex flow control
— Backpressure for half-duplex flow control
— Preamble generation and removal
— Automatic 32-bit CRC generation and checking
— Automatic payload padding and pad removal
— Loop-back modes
„ Flexible address filtering modes
— One 48-bit perfect address
— 64 hash-filtered multicast addresses
— Pass all multicast
— Promiscuous mode
— Inverse filtering
— Pass all incoming with status report
— Disable reception of broadcast packets
„ Integrated 10/100 Ethernet PHY
— Supports HP Auto-MDIX
— Auto-negotiation
— Supports energy-detect power down
„ High-Performance host bus interface
— Simple, SRAM-like interface
— 32 or 16-bit data bus
— 16Kbyte FIFO with flexible TX/RX allocation
— One configurable host interrupt
„ Miscellaneous features
— Low-profile, green, lead-free 100-pin TQFP package
— Integrated 1.8V regulator
— General Purpose Timer
— Optional EEPROM interface
— Support for 3 status LEDs multiplexed with
Programmable GPIO signals
„ Single 3.3V Power Supply with 5V tolerant I/O
„ 0 to 70°C Commercial Temperature Support
* Third-party brands and names are the property of their respective
owners.
SMSC LAN9218
DATASHEET
Revision 1.5 (07-18-06)

1 page




LAN9218 pdf
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
5.3.5 BYTE_TEST—Byte Order Test Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.3.6 FIFO_INT—FIFO Level Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
5.3.7 RX_CFG—Receive Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
5.3.8 TX_CFG—Transmit Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
5.3.9 HW_CFG—Hardware Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
5.3.10 RX_DP_CTRL—Receive Datapath Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.3.11 RX_FIFO_INF—Receive FIFO Information Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.3.12 TX_FIFO_INF—Transmit FIFO Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.3.13 PMT_CTRL— Power Management Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3.14 GPIO_CFG—General Purpose IO Configuration Register . . . . . . . . . . . . . . . . . . . . . . . 83
5.3.15 GPT_CFG-General Purpose Timer Configuration Register . . . . . . . . . . . . . . . . . . . . . . 84
5.3.16 GPT_CNT-General Purpose Timer Current Count Register . . . . . . . . . . . . . . . . . . . . . . 85
5.3.17 WORD SWAP—Word Swap Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
5.3.18 FREE_RUN—Free-Run 25MHz Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5.3.19 RX_DROP– Receiver Dropped Frames Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
5.3.20 MAC_CSR_CMD – MAC CSR Synchronizer Command Register . . . . . . . . . . . . . . . . . 87
5.3.21 MAC_CSR_DATA – MAC CSR Synchronizer Data Register . . . . . . . . . . . . . . . . . . . . . 87
5.3.22 AFC_CFG – Automatic Flow Control Configuration Register . . . . . . . . . . . . . . . . . . . . . 88
5.3.23 E2P_CMD – EEPROM Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.3.24 E2P_DATA – EEPROM Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
5.4 MAC Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
5.4.1 MAC_CR—MAC Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
5.4.2 ADDRH—MAC Address High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5.4.3 ADDRL—MAC Address Low Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
5.4.4 HASHH—Multicast Hash Table High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.4.5 HASHL—Multicast Hash Table Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.4.6 MII_ACC—MII Access Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.4.7 MII_DATA—MII Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
5.4.8 FLOW—Flow Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
5.4.9 VLAN1—VLAN1 Tag Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.4.10 VLAN2—VLAN2 Tag Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
5.4.11 WUFF—Wake-up Frame Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.4.12 WUCSR—Wake-up Control and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
5.5 PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
5.5.1 Basic Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
5.5.2 Basic Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.5.3 PHY Identifier 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
5.5.4 PHY Identifier 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.5.5 Auto-negotiation Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.5.6 Auto-negotiation Link Partner Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
5.5.7 Auto-negotiation Expansion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.5.8 Mode Control/Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
5.5.9 Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
5.5.10 Special Control/Status Indications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
5.5.11 Interrupt Source Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.5.12 Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
5.5.13 PHY Special Control/Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Chapter 6 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.1 Host Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.1.1 Special Restrictions on Back-to-Back Write/Read Cycles . . . . . . . . . . . . . . . . . . . . . . . 113
6.1.2 Special Restrictions on Back-to-Back Read Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
6.2 PIO Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.3 PIO Burst Reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.4 RX Data FIFO Direct PIO Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
SMSC LAN9218
5
DATASHEET
Revision 1.5 (07-18-06)

5 Page





LAN9218 arduino
High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
1.2 Internal Block Overview
This section provides an overview of each of these functional blocks as shown in Figure 1.2, "Internal
Block Diagram".
+3.3V
25MHz
EEPROM
(Optional)
PME
Wakup Indicator
Power Management
3.3V to 1.8V
Regulator
PLL
EEPROM
Controller
SRAM I/F
IRQ
FIFO_SEL
Host Bus Interface
(HBI)
PIO Controller
Interrupt
Controller
GP Timer
2kB to 14kB
Configurable TX FIFO
TX Status FIFO
RX Status FIFO
2kB to 14kB
Configurable RX FIFO
10/100
Ethernet
MAC
MIL - RX Elastic
Buffer - 128 bytes
MIL - TX Elastic
Buffer - 2K bytes
10/100
Ethernet
PHY
LAN
1.3
1.4
Figure 1.2 Internal Block Diagram
10/100 Ethernet PHY
The LAN9218 integrates an IEEE 802.3 physical layer for twisted pair Ethernet applications. The PHY
can be configured for either 100 Mbps (100Base-TX) or 10 Mbps (10Base-T) Ethernet operation in
either full or half duplex configurations. The PHY block supports HP Auto-MDIX and auto-negotiation.
Minimal external components are required for the utilization of the Integrated PHY.
10/100 Ethernet MAC
The transmit and receive data paths are separate within the MAC allowing the highest performance
especially in full duplex mode. The data paths connect to the PIO interface Function via separate
busses to increase performance. Payload data as well as transmit and receive status is passed on
these busses.
A third internal bus is used to access the MAC’s Control and Status Registers (CSR’s). This bus is
accessible from the host through the PIO interface function.
On the backend, the MAC interfaces with the internal 10/100 PHY through a the MII (Media
Independent Interface) port internal to the LAN9218. The MAC CSR's also provides a mechanism for
accessing the PHY’s internal registers through the internal SMI (Serial Management Interface) bus.
SMSC LAN9218
11
DATASHEET
Revision 1.5 (07-18-06)

11 Page







PáginasTotal 70 Páginas
PDF Descargar[ Datasheet LAN9218.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
LAN9210Small Form Factor Single- Chip Ethernet ControllerSMSC Corporation
SMSC Corporation
LAN9215Highly Efficient 10/100 Ethernet ControllerSMSC Corporation
SMSC Corporation
LAN9215IHighly Efficient Single-Chip 10/100 Ethernet ControllerSMSC Corporation
SMSC Corporation
LAN921716-bit High-Performance Single-Chip 10/100 Ethernet ControllerSMSC Corporation
SMSC Corporation

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar