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PDF FAN5099 Data sheet ( Hoja de datos )
| Número de pieza | FAN5099 | |
| Descripción | Wide Frequency Synchronous Buck PWM AND LDO Controller | |
| Fabricantes | Fairchild Semiconductor | |
| Logotipo |  |
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FAN5099 Wide Frequency Synchronous Buck
PWM & LDO Controller
Decemeber 2006
Features
■ General Purpose PWM Regulator and LDO Controller
■ Input Voltage Range: 3V to 24V
■ Output Voltage Range: 0.8V to 15V
■ VCC
– 5V
– Shunt Regulator for 12V Operation
■ Support for Ceramic Cap on PWM Output
■ Programmable Current Limit for PWM Output
■ Wide Programmable Switching Frequency Range
(50kHz to 600kHz)
■ RDS(ON) Current Sensing
■ Internal Synchronous Boot Diode
■ Soft-Start for both PWM and LDO
■ Multi-Fault Protection with Optional Auto-restart
■ 16-Pin TSSOP Package
Applications
■ High-Efficiency (80+) Computer Power Supplies
■ PC/Server Motherboard Peripherals
– VCC_MCH (1.5V), VDDQ (1.5V) and
VTT_GTL (1.25V)
■ Power Supply for
– FPGA, DSP, Embedded Controllers, Graphic Card
Processor, and Communication Processors
■ High-Power DC-to-DC Converters
Related Application Notes
■ AN-6020 FAN5099 Component Calculation and
Simulation Tools
■ AN-6005 Synchronous Buck MOSFET Loss
Calculations with Excel Model
Description
The FAN5099 combines a high-efficiency pulse-width
modulated (PWM) controller and an LDO (Low DropOut)
linear regulator controller. The PWM controller is
designed to operate over a wide frequency range (50kHz
to 600kHz) to accommodate a variety of applications.
Synchronous rectification provides high efficiency over a
wide range of load currents. Efficiency is further
enhanced by using the low-side MOSFET’s RDS(ON) to
sense current. In addition, the capability to operate at low
switching frequencies provides opportunities to boost
power supply efficiency by reducing switching losses and
gain cost savings using low-cost materials, such as pow-
dered iron cores, on the output inductor.
Both the linear and PWM regulator soft-start are con-
trolled by a single external capacitor, to limit in rush cur-
rent from the supply when the regulators are first
enabled. Current limit for PWM is also programmable.
The FAN5099’s ability to handle wide input voltage
ranges makes this controller suitable for power solutions
in a wide range of applications involving conversion input
voltages from Silver box, battery, and adapters. The
PWM regulator employs a summing-current-mode con-
trol with external compensation to achieve fast load tran-
sient response and provide system design optimization.
FAN5099 is offered in both industrial temperature grade
(-40°C to +85°C) as well as commercial temperature
grade (-10°C to +85°C).
Ordering Information
Part Number
FAN5099MTCX
FAN5099EMTCX
FAN5099MX
FAN5099EMX
Operating Temp. Range
-10°C to +85°C
-40°C to +85°C
-10°C to +85°C
-40°C to +85°C
Pb-Free
Yes
Yes
Yes
Yes
Package
16-Lead TSSOP
16-Lead TSSOP
16-Lead SOIC
16-Lead SOIC
Packing Method
Tape and Reel
Tape and Reel
Tape and Reel
Tape and Reel
Qty/Reel
2500
2500
2500
2500
Note: Contact Fairchild sales for availability of other package options.
© 2006 Fairchild Semiconductor Corporation
FAN5099 Rev. 1.1.3
www.fairchildsemi.com
1 page  
Electrical Characteristics
tUontlheessfuollthaemrwbiiesentnoopteedra,tVinCgCte=m5pVe, rTaAtu=re25ra°nCg,eu.s(4in,5g) the circuit in Figure 1. The ‘•’ denotes that the specifications apply
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
Supply Current
IVCC VCC Current (Quiescent)
HDRV, LDRV Open
• 2.6 3.2 3.8 mA
IVCC(SD) VCC Current (Shutdown)
EN = 0V, VCC = 5.5V
•
200 400 μA
IVCC(OP)
VSHUNT
VCC Current (Operating)
VCC Voltage(6)
EN = 5V, VCC = 5.0V,
QFET = 20nC, FSW = 200kHz
Sinking 1mA to 100mA at VCC Pin
10 15 mA
5.4 5.9 V
Under-Voltage Lockout (UVLO)
UVLO(H)
UVLO(L)
Rising VCC UVLO Threshold
Falling VCC UVLO Threshold
VCC UVLO Threshold
Hysteresis
• 4.00
• 3.60
4.25
3.75
0.5
4.50
4.00
V
V
V
Soft-Start
ISS Current
VLDOSTART LDO Start Threshold
VSSOK PWM Protection Enable
Threshold
10 μA
2.2 V
1.2 V
Oscillator
FOSC Frequency
R(T) = 25.5KΩ ± 1%
R(T) = 199KΩ ± 1%
R(T) = Open
240 300 360 kHz
60 80 100 kHz
50 kHz
Operating Frequency Range
40 600 kHz
ΔVRAMP Ramp Amplitude
(Peak-to-Peak)
R(RAMP) = 330KΩ
0.4 V
Minimum On Time
f = 200kHz
200 ns
Reference
VREF
Reference Voltage
(Measured at FB Pin)
Current Amplifier Reference
(at SW node)
TA = 0°C to 70°C
TA = -40°C to 85°C
• 790 800 810 mV
• 788 800 812 mV
160 mV
Error Amplifier
DC Gain
80 dB
GBWP Gain-BW Product
25 MHz
S/R Slew Rate
10pF across COMP to GND
8 V/μS
Output Voltage Swing
No Load
• 0.5
4.0 V
IFB FB Pin Source Current
Gate Drive
μA
RHUP
RHDN
RLUP
RLDN
HDRV Pull-up Resistor
HDRV Pull-down Resistor
LDRV Pull-up Resistor
LDRV Pull-down Resistor
Sourcing
Sinking
Sourcing
Sinking
• 1.8 3.0 Ω
• 1.8 3.0 Ω
• 1.8 3.0 Ω
• 1.2 2.0 Ω
© 2006 Fairchild Semiconductor Corporation
FAN5099 Rev. 1.1.3
5
www.fairchildsemi.com
5 Page 
PWM Operation
Refer to Figure 21 for the PWM control mechanism. The
FAN5099 uses the summing mode method of control to
generate the PWM pulses. The amplified output of the
current-sense amplifier is summed with an internally
generated ramp and the combined signal is amplified
and compared with the output of the error amplifier to get
the pulse width to drive the high-side MOSFET. The
sensed current from the previous cycle is used to modu-
late the output of the summing block. The output of the
summing block is also compared against the voltage
threshold set by the RLIM resistor to limit the inductor cur-
rent on a cycle-by-cycle basis. The controller facilitates
external compensation for enhanced flexibility.
Initialization
When the PWM is disabled, the SW node is connected
to GND through an internal 500Ω MOSFET to slowly dis-
charge the output. As long as the PWM controller is
enabled, this internal MOSFET remains OFF.
Soft-Start (PWM and LDO)
When VCC exceeds the UVLO threshold and EN is high,
the circuit releases SS and enables the PWM regulator.
The capacitor connected to the SS pin and GND is
charged by a 10µA internal current source, causing the
voltage on the capacitor to rise. When this voltage
exceeds 1.2V, all protection circuits are enabled. When
this voltage exceeds 2.2V, the LDO output is enabled.
The input to the error amplifier at the non-inverting pin is
clamped by the voltage on the SS pin until it crosses the
reference voltage.
The time it takes the PWM output to reach regulation
(TRise) is calculated using the following equation:
TRISE = 8 × 10–2 × CSS (CSS is in μf)
(EQ. 1)
Oscillator Clock Frequency (PWM)
The clock frequency on the oscillator is set using an
external resistor, connected between R(T) pin and
ground. The frequency follows the graph, as shown in
Figure 18. The minimum clock frequency is 50kHz,
which is when R(T) pin is left open. Select the value of
R(T) as shown in the equation below. This equation is
valid for all FOSC > 50kHz:
R(t) = 6----.-2----5-----×----F----O--4--S---×-C----1-–--0--2--7--.-9----9----×-----1----0---5- kΩ
where, FOSC is in Hz.
For example, for FOSC = 80kHz, R(t) = 199kΩ.
(EQ. 2)
RRAMP Selection and Feedforward Operation
The FAN5099 provides for input voltage feedforward
compensation through RRAMP. The value of RRAMP effec-
tively changes the slope of the internal ramp, minimizing
the variation of the PWM modulator gain when input volt-
age varies. The RRAMP effect on the current limit is
explained in later sections. The RRAMP value can be
approximated using the following equation:
RRAMP = 6---V-.-3--(--I×--N-1--,-0-n--–-o--8-m---×-)---–-F----O1---.-S-8--C-- KΩ
(EQ. 3)
where FOSC is in Hz. For example, for FOSC = 80kHz and
VIN = 12V, RRAMP = 2MΩ.
Gate Drive Section
The adaptive gate control logic translates the internal
PWM control signal into the MOSFET gate drive signals
and provides necessary amplification, level shifting, and
shoot-through protection. It also has functions that help
optimize the IC performance over a wide range of oper-
ating conditions. Since the MOSFET switching time can
vary dramatically from device to device and with the
input voltage, the gate control logic provides adaptive
dead time by monitoring the gate-to-source voltages of
both upper and lower MOSFETs. The lower MOSFET
drive is not turned on until the gate-to-source voltage of
the upper MOSFET has decreased to less than approxi-
mately 1V. Similarly, the upper MOSFET is not turned on
until the gate-to-source voltage of the lower MOSFET
has decreased to less than approximately 1V. This
allows a wide variety of upper and lower MOSFETs to be
used without a concern for simultaneous conduction, or
shoot-through.
A low impedance path between the driver pin and the
MOSFET gate is recommended for the adaptive dead-
time circuit to work properly. Any delay along this path
reduces the delay generated by the adaptive dead-time
circuit, thereby increasing the chances for shoot-through.
Protection
In the FAN5099, the converter is protected against over-
load, short-circuit, over-voltage, and under-voltage con-
ditions. All of these extreme conditions generate an
internal “fault latch” which shuts down the converter. For
all fault conditions, both the high-side and the low-side
drives are off, except in the case of OVP, where the low-
side MOSFET is turned on until the voltage on the FB pin
goes below 0.4V. The fault latch can be reset either by
toggling the EN pin or recycling VCC to the chip.
Over-Current Limit (PWM)
The PWM converter is protected against overloading
through a cycle-by-cycle current limit set by selecting
RILIM resistor. An internal 10µA current source sets the
threshold voltage for the output of the summing amplifier.
When the summing amplifier output exceeds this thresh-
old level, the current limit comparator trips and the PWM
starts skipping pulses. If the current limit tripping occurs
for 16 continuous clock cycles, a fault latch is set and the
© 2006 Fairchild Semiconductor Corporation
FAN5099 Rev. 1.1.3
11
www.fairchildsemi.com
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet FAN5099.PDF ] | |
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