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PDF ZL50052 Data sheet ( Hoja de datos )

Número de pieza ZL50052
Descripción 8 K Channel Digital Switch
Fabricantes Zarlink Semiconductor 
Logotipo Zarlink Semiconductor Logotipo



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Features
• 8,192 channel x 8,192 channel non-blocking
unidirectional switching. The Backplane and
Local inputs and outputs can be combined to form
a non-blocking switching matrix with 16 input
streams and 16 output streams
• 4,096 channel x 4,096 channel non-blocking
Backplane input to Local output stream switch
• 4,096 channel x 4,096 channel non-blocking
Local input to Backplane output stream switch
• 4,096 channel x 4,096 channel non-blocking
Backplane input to Backplane output switch
• 4,096 channel x 4,096 channel non-blocking
Local input to Local output stream switch
• Backplane port accepts 8 input and 8 output ST-
BUS streams with data rate of 32.768 Mbps
• Local port accepts 8 input and 8 output ST-BUS
streams with data rate of 32.768 Mbps
• Exceptional input clock jitter tolerance (14 ns)
• Per-stream bit delay for Local and Backplane
input streams
• Per-stream advancement for Local and
Backplane output streams
ZL50052
8 K Channel Digital Switch with High Jitter
Tolerance, Single Rate (32 Mbps),
and 16 Inputs and 16 Outputs
Data Sheet
December 2003
Ordering Information
ZL50052GAC 196 ball PBGA
-40°C to +85°C
• Constant 2-frame throughput delay for frame
integrity
• Per-channel high impedance output control for
Local and Backplane streams
• Per-channel driven-high output control for Local
and Backplane streams
• Per-channel message mode for Local and
Backplane output streams
• Connection memory block programming for fast
device initialization
• Automatic selection between ST-BUS and GCI-
Bus operation
• Non-multiplexed Motorola microprocessor
interface
VDD_IO VDD_CORE
VSS (GND)
RESET
ODE
BSTi0-7
Backplane Data Memories
(4,096 channels)
Local
Interface
LSTi0-7
BSTo0-7
Backplane
Interface
Backplane
Connection Memory
(4,096 locations)
Local
Connection Memory
(4,096 locations)
Local
Interface
LSTo0-7
BORS
FP8i
C8i
Input
Timing Unit
PLL
Local Data Memories
(4,096 channels)
Microprocessor Interface
and Internal Registers
Output
Timing
Unit
Test Port
LORS
FP8o
FP16o
C8o
C16o
VDD_PLL
DS CS R/W A14-0 DTA D15-0 TMS TDi TDo TCK TRST
Figure 1 - ZL50052 Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.

1 page




ZL50052 pdf
ZL50052
Data Sheet
Table of Contents
13.1 Control Register (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
13.2 Block Programming Register (BPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
13.3 Local Input Bit Delay Registers (LIDR0 to LIDR7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
13.3.1 Local Input Delay Bits 4-0 (LID[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
13.4 Backplane Input Bit Delay Registers (BIDR0 to BIDR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
13.4.1 Backplane Input Delay Bits 4-0 (BID[4:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
13.5 Local Output Advancement Registers (LOAR0 to LOAR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
13.5.1 Local Output Advancement Bits 1-0 (LOA1-LOA0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
13.6 Backplane Output Advancement Registers (BOAR0 - BOAR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.6.1 Backplane Output Advancement Bits 1-0 (BOA1-BOA0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.7 Memory BIST Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13.8 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
14.0 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
15.0 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5
Zarlink Semiconductor Inc.

5 Page





ZL50052 arduino
ZL50052
Data Sheet
Pin Description (continued)
Pin Name
ZL50052
Package
Coordinates
(196 ball
PBGA)
Description
LORS
H13 Local Output Reset State (5 V Tolerant Input with Internal Pull-down)
When this input is LOW, the device will initialize with the LSTo0-7 outputs
driven high. Following initialization, the Local stream outputs are always
active.
When this input is HIGH, the device will initialize with the LSTo0-7 outputs at
high impedance. Following initialization, the Local stream outputs may be set
active or high impedance using the ODE pin or on a per-channel basis with
the LE bit in the Local Connection Memory.
LSTo0-7
B13, B14, D14,
C14, D12, E14,
D13, E13
Local Serial Output Streams 0 to 7 (5 V Tolerant Three-state Outputs
with Slew-Rate Control)
These pins output serial TDM data streams at a fixed data rate of
32.768 Mbps (with 512 channels per stream).
Refer to the descriptions of the LORS and ODE pins for control of the output
HIGH or high impedance state.
Microprocessor Port Signals
A0 - A14
B1, B4, B5, D5,
A3, A4, C6, B6,
A5, A6, C7, B7,
A7, A8, B8
Address 0 - 14 (5 V Tolerant Inputs)
These pins form the 15-bit address bus to the internal memories and
registers.
A0 = LSB
D0 - D15
N7, P7, P6, N6,
P5, M6, P4, N5,
P3, P2, N3, N4,
M5, N2, M4, M3
Data Bus 0 - 15 (5 V Tolerant Inputs/Outputs with Slew-Rate Control)
These pins form the 16-bit data bus of the microprocessor port.
D0 = LSB
CS A10 Chip Select (5 V Tolerant Input)
Active LOW input used by the microprocessor to enable the microprocessor
port access
Note that a minimum of 30 ns must separate the de-assertion of DTA (to
high) and the assertion of CS and/or DS to initiate the next access.
DS C8 Data Strobe (5 V Tolerant Input)
This active LOW input works in conjunction with CS to enable the
microprocessor port read and write operations.
Note that a minimum of 30 ns must separate the de-assertion of DTA (to
high) and the assertion of CS and/or DS to initiate the next access.
R/W A9 Read/Write (5 V Tolerant Input)
This input controls the direction of the data bus lines (D0-D15) during a
microprocessor access.
DTA
D9 Data Transfer Acknowledgment (5 V Tolerant Three-state Output)
This active LOW output indicates that a data bus transfer is complete. A
pull-up resistor is required to hold a HIGH level.
Note that a minimum of 30 ns must separate the de-assertion of DTA (to
high) and the assertion of CS and/or DS to initiate the next access.
11
Zarlink Semiconductor Inc.

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