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PDF MAS9316 Data sheet ( Hoja de datos )
| Número de pieza | MAS9316 | |
| Descripción | 16-BIT DAC | |
| Fabricantes | MAS | |
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DA9316.003
March 23, 2005
MAS9316
16-BIT DAC
· +/- 0.006% DNL and INL
· No Laser Trimming
· Fast Interface Timing
DESCRIPTION
The MAS9316 is a 16-bit, monolithic CMOS, multiplying
digital-to-analog converter (DAC ) designed for direct
microprocessor interface. Its high relative accuracy and
monotonicity is achieved without laser trimming. This is
made possible by the use of highly accurate, low TCR
thin film resistor process and a 4 MSB to 15 decoding
design technique. Hidden errors are eliminated by
testing all the 65536 different input codes.The device
FEATURES
· Linearity TC 0.5 ppm/C
· 2 kV ESD Protection on Digital Inputs
· D4 MSB's Decoded
· All 65536 Codes Tested
· Monolithic CMOS Replacement for SIPEX
· DAC 9331-16-4 and SP9316C-4
· 24-pin PDIP Package
offers advantages like high stability over time and
temperature and low sensitivity to output amplifier offset
combined to excellent performance-to-cost ratio. The
fast input data latches are designed as two 8-bit
segments providing data storage when latched or
transparent operation when unlatched. All digital inputs
have high ESD protection up to 2 kV.
APPLICATION
· Audio applications
· Instrumentation
· uP Controlled systems
BLOCK DIAGRAM
VDD
VREF
BIT1/
...MSB
BIT16/
LSB
LBE
HBE
8-BIT
INPUT
REG.
8-BIT
INPUT
REG.
16-BIT DAC
DGND
IO2
RFB
IO1
1
1 page  
DA9316.003
March 23, 2005
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for design guidance only and are subject to sample testing only. VDD=+15V,
VREF=10V, IO1=IO2=DGND=0V except where stated. Output Amp is HOS-050.
(test conditions Ta=+25C)
Parameter
Symbol
Conditions
Min Typ
Max Units
Propagation Delay
tPD IO1 load R=100Ω, Cext=13pF
All Data Inputs 0V to VDD or
VDD to 0V
From 50% digital input change
to 90% of final analog output.
300
ns
CURRENT SETTLING
ts
TIMESettling
1.5 µS
Major Code Transition
to +0.01% FSR (strobed).
0111111111111111 to
1000000000000000 or
1000000000000000 to
0111111111111111
Full Scale Transition
All Data Inputs 0V to VDD or
3.0
µs
VDD to 0V
OUTPUT CAPACITANCE
CIO1 (Pin 16)170
CIO2 (Pin 15)
CIO1 (Pin 16)
CIO2 (Pin 15)
Co
Digital inputs VIH
Digital inputs VIH
Digital inputs VIL
Digital inputs VIL
170 pF
30 pF
80 pF
100 pF
Digital to Analog Glitch
Energy
Q VREF =0V
DAC register alternately loaded
with all 0s and all 1s
250
nVs
Multiplying Feedthrough
Error at IO1
FT VREF=20Vpp; f=10kHz sine wave
VREF=20Vpp, f=1kHz sine wave
3.0
0.3
mVpp
mVpp
Power Supply Rejection
Ratio
PSRR
VDD = 14 to 16V
±0.0001 ±0.002 %/%
TIMING DIAGRAM
DATA
LATCH
OUTPUT
t1
t2
t1 = Data Setup Time (80ns)
t2 = Strobe Width (80ns)
t3 = Settling Time (2us typical)
t1
t2
t3
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MAS9316.PDF ] | |
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