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PDF ZL38002 Data sheet ( Hoja de datos )
| Número de pieza | ZL38002 | |
| Descripción | Digital Echo Canceller | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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ZL38002
Digital Echo Canceller for Hands Free
Communication
Data Sheet
Features
• 112 ms acoustic echo canceller
• Up to 12 dB of noise reduction
• Works with low cost voice codec. ITU-T G.711 or
signed mag µ/A-Law, or linear 2’s compliment
• Each port may operate independently in
companded format or linear format
• Advanced NLP design - full duplex speech with
no switched loss on audio paths
• Fast re-convergence time: tracks changing echo
environment quickly
• Adaptation algorithm converges even during
Double-Talk
• Designed for exceptional performance in high
background noise environments
• Provides protection against narrow-band signal
divergence
• Howling prevention stops uncontrolled oscillation
in high loop gain conditions
• Programmable offset nulling of all PCM channels
• Serial micro-controller interface
• Idle channel noise suppression
• ST-BUS, GCI, or variable-rate SSI PCM
interfaces
January 2007
Ordering Information
ZL38002QDG
ZL38002QDG1
ZL38002DGE1
ZL38002DGF1
48 Pin TQFP
48 Pin TQFP*
36 Pin QSOP*
36 Pin QSOP*
Trays
Trays
Tubes, Bake & Drypack
Tape & Reel,
Bake & Drypack
*Pb Free Matte Tin
-40°C to 85°C
• User gain control provided for speaker path
(-24 dB to +21 dB in 3 dB steps)
• Adjustable gain pads from -24 dB to +21 dB at
Xin, Sin and Sout to compensate for different
system requirements
• AGC on speaker path
• Handles up to -6 dB acoustic echo return loss
(with the appropriate gain pad settings)
• Transparent data transfer and mute options
• 20 MHz master clock operation
• Low power mode during PCM Bypass
• Bootloadable for future factory software upgrades
• 2.7 V to 3.6 V supply voltage; 5 V-tolerant inputs
Sin
MD1
MD2
Rout
µ/A-Law/
Linear
HP
Filter
NBSD
Gain
Pad
S1 + + S2
-
ADV
NLP
Noise
Reduction
Adaptive
Filter
Gain
Pad
R1
CONTROL
UNIT
Double
Talk
Detector
R1
Gain
Pad
Limiter
Linear/
µ/A-Law
Program
RAM
Program
ROM
Micro
Interface
NBSD
Howling
Controller
Linear/
µ/A-Law
-24 -> +21dB
AGC
User
Gain
Limiter
HP
Filter
µ/A-Law/
Linear
VDD
VSS
RESET FORMAT ENA2
ENA1
LAW
F0i BCLK/C4i MCLK
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2005-2007, Zarlink Semiconductor Inc. All Rights Reserved.
Sout
DATA1
DATA2
SCLK
CS
Rin
1 page  
ZL38002
Data Sheet
Pin Description (continued)
QSOP
Pin #
TQFP
Pin #
Name
Description
25
26
27, 28
29
30
27
29
30, 31
33
34
F0i Frame Pulse (Input). In ST-BUS (or GCI) operation, this is an active-low
(or active-high) frame alignment pulse, respectively. SSI operation is
enabled by connecting this pin to Vss.
BCLK/C4i Bit Clock/ST-BUS Clock (Input). In SSI operation, BCLK pin is a 128 kHz
to 4.096 MHz bit clock. This clock must be synchronous with ENA1 and
ENA2 enable strobes.
In ST-BUS or GCI operation, C4i pin must be connected to the 4.096 MHz
(C4) system clock.
IC Internal Connection (Input). Tie to Vss.
VSS2 Digital Ground (Input). Nominally 0 volts.
VDD2 Positive Power Supply (Input). Nominally 3.3 volts (tie together with
VDD).
31 35 VSS Digital Ground (Input). Nominally 0 volts (tie together with VSS2).
33 38 MCLK2 Master Clock (Input). Nominal 20 MHz master clock (tie together with
MCLK).
34,35,36 39, 40, 41
IC Internal Connection (Input). Tie to Vss.
15, 16, 21,
32
1, 4, 10, 12,
14, 15, 18,
20, 22, 25,
28, 32, 36,
37, 42, 44
NC No Connect (Output). This pin should be left unconnected.
5
Zarlink Semiconductor Inc.
5 Page 
ZL38002
Data Sheet
2.8 Limiters
To prevent clipping in the echo paths, two limiters with variable thresholds are provided at the outputs.
2.9 User Gain
The user gain function provides the ability for users to adjust the audio gain on all paths. This gain is adjustable
from -24 dB to +21 dB in 3 dB steps for the Sout and Rout paths. It is important to use ONLY this user gain function
to adjust the speaker volume. The user gain function in the ZL38002 is optimally placed outside the echo path such
that no reconvergence is necessary after gain changes, avoiding a burst of each overtime the speaker gain is
changed.
2.10 AGC
The AGC function is provided to limit the volume in the speaker path. The gain of the speaker path is automatically
reduced during the following conditions:
• When clipping of the receive signal occurs
• When initial convergence of the acoustic echo canceller detects unusually large echo return
• When howling is detected
The AGC can be disabled by setting the AGC- bit to 1 in MC control register
2.11 Programmable Gain Pad
The ZL38002 has three gain pads located at Sin, Sout and at the adaptive filter (Xin). These gain pads are intended
to be set once during initialization and not be used as dynamic gain adjustments. The purpose of theses gainpads
are to help fine tune the performance of the acoustic echo canceller for a particular system.
For example, the gain pad can be used to improve the subjective quality in low ERL environments. The ZL38002
can cancel echo with a ERL as low as 0 dB (attenuation from Rout to Sin). In many hand free applications, the ERL
can be low (or negative). This is due to both speaker and microphone gain setting. The speaker gain has to be set
high enough for the speaker to be heard properly and the microphone gain needs to be set high enough to ensure
sufficient signal is sent to the far end. If the ERL (Acoustic Attenuation - speaker gain - microphone gain) is greater
than 0 dB, then the echo canceller cannot cancel echo. To overcome this limitation, the gain pad at Sin and Sout
can be used to lower the Sin level (and therefore the ERL) by 6 dB, perform the echo cancellation then amplify it at
Sout by 6 dB. This will have the effect having 0dB gain between Sin and Sout for double talk signals while injecting
a additional 6 dB attenuation for the echo return. It is important to reduce the DTDT threshold (Page 0 address 30)
to match the Sin/Sout gain settings.
The gain can be accessed through Customer Gain Control Registers 1 - 2 (Page 0, Address 1CH - 1DH).
2.12 Mute Function
A pcm mute function is provided for independent control of the Receive and Send audio paths. Setting the MUTE_R
or MUTE_S bit in the MC register, causes quiet code to be transmitted on the Rout or Sout paths respectively. The
ZL38002 has an optional DC offset control. The user can add a positive offset to the mute value. This is controlled
through the DC offset register (Page 0, Address 03h)
Quiet code is defined according to the following table.
11
Zarlink Semiconductor Inc.
11 Page | ||
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