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PDF ZL30122 Data sheet ( Hoja de datos )

Número de pieza ZL30122
Descripción SONET/SDH Low Jitter Line Card Synchronizer
Fabricantes Zarlink Semiconductor 
Logotipo Zarlink Semiconductor Logotipo



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No Preview Available ! ZL30122 Hoja de datos, Descripción, Manual

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ZL30122
SONET/SDH
Low Jitter Line Card Synchronizer
Data Sheet
A full Design Manual is available to qualified customers.
To register, please send an email to
Features
• Synchronizes with standard telecom system
references and synthesizes a wide variety of
protected telecom line interface clocks that are
compliant with Telcordia GR-253-CORE and ITU-T
G.813
• Internal APLL provides standard output clock
frequencies up to 622.08 MHz with jitter < 3 ps
RMS suitable for GR-253-CORE OC-12 and G.813
STM-16 interfaces
• Programmable output synthesizer generates clock
frequencies from any multiple of 8 kHz up to
77.76 MHz in addition to 2 kHz
• Digital Phase Locked-Loop (DPLL) provides all the
features necessary for generating SONET/SDH
compliant clocks including automatic hitless
reference switching, automatic mode selection
(locked, free-run, holdover), and selectable loop
bandwidth
Ordering Information
May 2006
ZL30122GGG 64 Pin CABGA
Trays
ZL30122GGG2 64 Pin CABGA* Trays
*Pb Free Tin/Silver/Copper
-40oC to +85oC
• Provides 3 reference inputs which support clock
frequencies with any multiples of 8 kHz up to
77.76 MHz in addition to 2 kHz
• Provides 3 sync inputs for output frame pulse
alignment
• Generates several styles of output frame pulses
with selectable pulse width, polarity, and frequency
• Configurable input to output delay, and output to
output phase alignment
• Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
• Supports IEEE 1149.1 JTAG Boundary Scan
osco
osci
trst_b tck tdi tms tdo
Master
Clock
IEEE 1449.1
JTAG
ref0 ref2:0
ref1
ref2
sync0
sync1
sync2
sync2:0
Reference ref_&_sync_status
Monitors
dpll_lock dpll_holdover
diff_en
ref
DPLL
sync
SONET/SDH
APLL
Programmable
Synthesizer
diff_clk_p/n
sdh_clk
sdh_fp
p_clk
p_fp
int_b
SPI Interface
Controller &
State Machine
sck si so cs_b
rst_b
dpll_mod_sel
sdh_filter filter_ref0 filter_ref1
Figure 1 - Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved.

1 page




ZL30122 pdf
ZL30122
Data Sheet
List of Tables
Table 1 - DPLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4 - Output Clock and Frame Pulse Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 5 - Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5
Zarlink Semiconductor Inc.

5 Page





ZL30122 arduino
ZL30122
Data Sheet
1.3 Ref and Sync Inputs
There are three reference clock inputs (ref0 to ref2) available to the DPLL. Reference selection can be controlled
using a built-in state machine or set in a manual mode.The selected reference input is used to synchronize the
output clocks.
ref2:0
sync2:0
DPLL
Figure 3 - Reference and Sync Inputs
In addition to the reference inputs, the DPLL has three optional frame pulse synchronization inputs (sync0 to
sync2) used to align the output frame pulses. The syncn input is selected with its corresponding refn input, where n
= 0, 1, or 2. Note that the sync input cannot be used to synchronize the DPLL, it only determines the alignment of
the frame pulse outputs. An example of output frame pulse alignment is shown in Figure 4.
Without a frame pulse
signal at the sync input,
the output frame pulses
will align to any arbitrary
cycle of its associated
output clock.
n = 0, 1, 2
refn
syncn - no frame pulse signal present
diff_clk/sdh_clk/p_clk
sdh/p_fp
When a frame pulse
signal is present at the
sync input, the DPLL
will align the output
frame pulses to the
output clock edge that is
aligned to the input
frame pulse.
n = 0, 1, 2
refn
syncn
diff_clk/sdh_clk/p_clk
sdh_fp/p_fp
Figure 4 - Output Frame Pulse Alignment
11
Zarlink Semiconductor Inc.

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