PDF ZL30120 Data sheet ( Hoja de datos )

Número de pieza	ZL30120
Descripción	SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer
Fabricantes	Zarlink Semiconductor
Logotipo
Hay una vista previa y un enlace de descarga de ZL30120 (archivo pdf) en la parte inferior de esta página. Total 27 Páginas
No Preview Available ! www.DataSheet4U.com ZL30120 SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer Data Sheet A full Design Manual is available to qualified customers. To register, please send an email to [email protected]. Features • Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-1244-CORE, GR-253- CORE, ITU-T G.813, and compatible with ITU-T G.8261 (formerly G.pactiming) • Internal low jitter APLL provides SONET/SDH clocks including 6.48 MHz, 19.44 MHz, 38.88 MHz, 51.84 MHz and 77.76 MHz, or 25 MHz and 50 MHz Synchronous Ethernet output clocks • Programmable output synthesizers (P0, P1) generate general purpose clock frequencies from any multiple of 8 kHz up to 100 MHz • Jitter performance of <8 ps RMS on the low jitter APLL outputs, and <20 ps RMS on the programmable synthesizer outputs. • Provides 8 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz Ordering Information May 2006 ZL30120GGG 100 Pin CABGA Trays ZL30120GGG2 100 Pin CABGA Trays Pb Free Tin/Silver/Copper -40oC to +85oC • Provides two DPLLs which have independent modes of operation (locked, free-run, holdover) and optional hitless reference switching. • Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities • Provides 3 sync inputs for output frame pulse alignment • Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency • Configurable input to output delay, and output to output phase alignment • Supports IEEE 1149.1 JTAG Boundary Scan osco osci ref0 ref1 ref2 ref3 ref4 ref5 ref6 ref7 sync0 sync1 sync2 int_b trst_b tck tdi tms tdo dpll2_ref dpll1_hs_en dpll1_lock dpll1_holdover Master Clock IEEE 1449.1 JTAG ref7:0 sync2:0 Reference ref_&_sync_status Monitors DPLL2 ref ref DPLL1 sync fb_clk/fp P0 Synthesizer P1 Synthesizer Low Jitter APLL Feedback Synthesizer SPI Interface Controller & State Machine p0_clk0 p0_clk1 p0_fp0 p0_fp1 p1_clk0 p1_clk1 apll_clk0 apll_clk1 apll_fp0 apll_fp1 fb_clk sck si so cs_b rst_b dpll1_mod_sel1:0 apll_filter filter_ref0 filter_ref1 Figure 1 - Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved. 1 page ZL30120 Data Sheet List of Tables Table 1 - DPLL1 and DPLL2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 2 - Set of Pre-Defined Auto-Detect Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 3 - Set of Pre-Defined Auto-Detect Sync Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4 - Output Clock and Frame Pulse Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5 Zarlink Semiconductor Inc. 5 Page ZL30120 Data Sheet 1.0 Functional Description The ZL30120 Multi-Rate Line Card Synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. It incorporates two independent DPLLs, each capable of locking to one of eight input references and provides a wide variety of synchronized output clocks and frame pulses. 1.1 DPLL Features The ZL30120 provides two independently controlled Digital Phase-Locked Loops (DPLL1, DPLL2) for clock and/or frame pulse synchronization. DPLL1 is the main DPLL and is always enabled. To save on power, DPLL2 is disabled by default. For applications where DPLL2 is required, it must be enabled using the dpll_en bit of the dpll2_ctrl_0 register (0x2A). Table 1 shows a feature summary for both DPLLs. Feature DPLL1 DPLL2 Modes of Operation Free-run, Normal (locked), Holdover Free-run, Normal (locked), Holdover Loop Bandwidth User selectable: 14 Hz, 28 Hz, or wideband1 (890 Hz / 56 Hz / 14 Hz) Fixed: 14 Hz Phase Slope Limiting User selectable: 885 ns/s, 7.5 µs/s, 61 µs/s, or unlimited User selectable: 61 µs/s, or unlimited Pull-in Range Fixed: 130 ppm Fixed: 130 ppm Holdover Parameters Selectable Update Times: 26 ms, 1 s, 10 s, 60 s, and Selectable Holdover Post Filter BW: 18 mHz, 2.5 Hz, 10 Hz. Fixed Update Time: 26 ms No Holdover Post Filtering Holdover Frequency Accuracy Better than 1 ppb (Stratum 3E) initial frequency offset. Frequency drift depends on the 20 MHz external oscillator. Better than 50 ppb (Stratum 3) initial frequency offset. Frequency drift depends on the 20 MHz external oscillator. Reference Inputs Ref0 to Ref7 Ref0 to Ref7 Sync Inputs Sync0, Sync1, Sync2 Sync inputs are not supported. Input Reference Selection/Switching Automatic (based on programmable priority and revertiveness), or manual Automatic (based on programmable priority and revertiveness), or manual Hitless Ref Switching Can be enabled or disabled Can be enabled or disabled Output Clocks apll_clk0, apll_clk1, p0_clk0, p0_clk1, p1_clk0, p1_clk1, fb_clk. p0_clk0, p0_clk1, p1_clk0, p1_clk1. Output Frame Pulses apll_fp0, apll_fp1, p0_fp0, p0_fp1 p0_fp0, p0_fp1 not synchronized to sync synchronized to active sync reference. reference. External Pins Status Indicators Lock, Holdover None Table 1 - DPLL1 and DPLL2 Features 1. In the wideband mode, the loop bandwidth depends on the frequency of the reference input. For reference frequencies equal to or greater than 64 kHz, the loop bandwidth = 890 Hz. For reference frequencies equal to or greater than 8 kHz and less than 64 kHz, the loop bandwidth = 56 Hz. For reference frequencies equal to 2 kHz, the loop bandwidth is equal to 14 Hz. 11 Zarlink Semiconductor Inc. 11 Page

Páginas	Total 27 Páginas
PDF Descargar	[ Datasheet ZL30120.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
ZL30120	SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer	Zarlink Semiconductor
ZL30121	SONET/SDH Low Jitter System Synchronizer	Zarlink Semiconductor
ZL30122	SONET/SDH Low Jitter Line Card Synchronizer	Zarlink Semiconductor
ZL30123	Low Jitter Line Card Synchronizer	Zarlink Semiconductor

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar