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PDF ZL30111 Data sheet ( Hoja de datos )

Número de pieza ZL30111
Descripción POTS Line Card PLL
Fabricantes Zarlink Semiconductor 
Logotipo Zarlink Semiconductor Logotipo



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ZL30111
POTS Line Card PLL
Data Sheet
Features
January 2007
• Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or
19.44 MHz input
• Provides a range of clock outputs: 2.048 MHz,
4.096 MHz and 8.192 MHz
• Provides 2 styles of 8 kHz framing pulses
• Automatic entry and exit from freerun mode on
reference fail
Ordering Information
ZL30111QDG
ZL30111QDG1
64 Pin TQFP Trays, Bake & Drypack
64 Pin TQFP* Trays, Bake & Drypack
*Pb Free Matte Tin
-40°C to +85°C
Applications
• Provides DPLL lock and reference fail indication
• Synchronizer for POTS line cards
• DPLL bandwidth of 922 Hz for all rates of input
reference and 58 Hz for an 8 kHz input reference
• Rate convert NTR 8kHz or GPON physical
interface clock to TDM clock
• Less than 0.6 nspp intrinsic jitter on all output clocks Description
• 20 MHz external master clock source: clock
oscillator or crystal
The ZL30111 POTS line card PLL contains a digital
• Simple hardware control interface
phase-locked loop (DPLL), which provides timing and
synchronization for SLIC/CODEC devices.
The ZL30111 generates TDM clock and framing
signals that are phase locked to the input reference.
It helps ensure system reliability by monitoring its
reference for stability and by maintaining stable
output clocks during short periods when the
reference is unavailable.
REF
RST
OSCi
OSCo
REF_FAIL
LOCK
Reference
Monitor
State Machine
Master
Clock
Mode
Control
DPLL
C2o
C4
C8
F4
F8
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2007, Zarlink Semiconductor Inc. All Rights Reserved.

1 page




ZL30111 pdf
ZL30111
Data Sheet
1.2 Pin Description
Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Name
GND
VCORE
LOCK
REF_FAIL
IC
IC
IC
IC
IC
IC
IC
VCORE
GND
AVCORE
IC
IC
IC
IC
RST
OSCo
OSCi
IC
GND
NC
VDD
IC
Description
Ground. 0 V.
Positive Supply Voltage. +1.8 VDC nominal.
Lock Indicator (Output). This output goes to a logic high when the PLL is frequency
locked to the selected input reference.
Reference Failure Indicator (Output). A logic high at this pin indicates that the REF
reference frequency is exhibiting abrupt phase or frequency changes.
Internal Connection. Leave unconnected.
Internal Connection. Leave unconnected.
Internal Connection. Leave unconnected.
Internal Connection. Leave unconnected.
Internal Connection. Leave unconnected.
Internal Connection. Connect to GND.
Internal Connection. Connect to GND.
Positive Supply Voltage. +1.8 VDC nominal.
Ground. 0 V.
Positive Analog Supply Voltage. +1.8 VDC nominal.
Internal Connection. Leave unconnected.
Internal Connection. Connect to VDD.
Internal Connection. Connect to GND.
Internal Connection. Connect to GND.
Reset (Input). A logic low at this input resets the device. On power up, the RST pin
must be held low for a minimum of 300 ns after the power supply pins have reached
the minimum supply voltage. When the RST pin goes high, the device will transition
into a Reset state for 3 ms. In the Reset state all clock and frame pulse outputs will be
forced into high impedance.
Oscillator Master Clock (Output). For crystal operation, a 20 MHz crystal is connected
from this pin to OSCi. This output is not suitable for driving other devices. For clock
oscillator operation, this pin must be left unconnected.
Oscillator Master Clock (Input). For crystal operation, a 20 MHz crystal is connected
from this pin to OSCo. For clock oscillator operation, this pin must be connected to a
clock source.
Internal Connection. Leave unconnected.
Ground. 0 V.
No internal bonding Connection. Leave unconnected.
Positive Supply Voltage. +3.3 VDC nominal.
Internal Connection. Connect this pin to GND.
5
Zarlink Semiconductor Inc.

5 Page





ZL30111 arduino
ZL30111
Data Sheet
4.0 Measures of Performance
The following are some PLL performance indicators and their corresponding definitions.
4.1 Jitter
Timing jitter is defined as the high frequency variation of the clock edges from their ideal positions in time. Wander
is defined as the low-frequency variation of the clock edges from their ideal positions in time. High and low
frequency variation imply phase oscillation frequencies relative to some demarcation frequency. (Often 10 Hz or
20 Hz for DS1 or E1, higher for SONET/SDH clocks.) Jitter parameters given in this data sheet are total timing jitter
numbers, not cycle-to-cycle jitter.
4.2 Jitter Generation (Intrinsic Jitter)
Jitter generation is the measure of the jitter produced by the PLL and is measured at its output. It is measured by
applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Jitter is usually
measured with various band limiting filters depending on the applicable standards.
4.3 Jitter Transfer
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter
at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured
with various filters depending on the applicable standards.
4.4 Lock Time
This is the time it takes the PLL to frequency lock to the input signal. Phase lock occurs when the input signal and
output signal are aligned in phase with respect to each other within a certain phase distance (not including jitter).
Lock time is affected by many factors which include:
• initial input to output phase difference
• initial input to output frequency difference
• PLL loop filter bandwidth
The presence of input jitter makes it difficult to define when the PLL is locked as it may not be able to align its output
to the input within the required phase distance, dependent on the PLL bandwidth and the input jitter amplitude and
frequency.
11
Zarlink Semiconductor Inc.

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