|
|
PDF ZL30105 Data sheet ( Hoja de datos )
| Número de pieza | ZL30105 | |
| Descripción | T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ZL30105 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
ZL30105
T1/E1/SDH Stratum 3 Redundant System Clock
Synchronizer for AdvancedTCA™ and H.110
Data Sheet
Features
• Synchronizes to clock-and-sync-pair to maintain
minimal phase skew between the master-clock
and the redundant slave-clock
• Supports ITU-T G.813 option 1, G.823 for
2048 kbit/s and G.824 for 1544 kbit/s interfaces
• Supports Telcordia GR-1244-CORE Stratum
3/4/4E
• Supports ANSI T1.403 and ETSI ETS 300 011 for
ISDN primary rate interfaces
• Accepts three input references and synchronizes
to any combination of 2 kHz, 8 kHz, 1.544 MHz,
2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz
inputs
• Provides a range of clock outputs: 1.544 MHz
(DS1), 2.048 MHz (E1), 3.088 MHz, 16.384 MHz,
and 19.44 MHz (SDH), and either 4.096 MHz and
8.192 MHz or 32.768 MHz and 65.536 MHz, and a
choice of 6.312 MHz (DS2), 8.448 MHz (E2),
44.736 MHz (DS3) or 34.368 MHz (E3)
• Provides 5 styles of 8 kHz framing pulses and a
2 kHz multi-frame pulse
• Holdover frequency accuracy of 1x10-8
• Selectable loop filter 1.8 Hz, 3.6 Hz or 922 Hz
• Less than 24 psrms intrinsic jitter on the 19.44 MHz
output clock, compliant with GR-253-CORE OC-3
and G.813 STM-1 specifications
November 2005
Ordering Information
ZL30105QDG 64 pin TQFP Trays
ZL30105QDG1 64 pin TQFP* Trays Bake & Drypack
* Pb Free Matte Tin
-40°C to +85°C
• Less than 0.6 nspp intrinsic jitter on all output
clocks and frame pulses
• Manual or Automatic hitless reference switching
between any combination of valid input reference
frequencies
• Provides Lock, Holdover and selectable Out of
Range indication
• Simple hardware control interface
• Selectable external master clock source: Clock
Oscillator or Crystal
Applications
• Synchronization and timing control for multi-trunk
SDH and T1/E1 systems such as DSLAMs,
Gateways and PBXs
• Clock and frame pulse source for
AdvancedTCA™- and other time division
multiplex (TDM) buses
OSCi OSCo TIE_CLR
FASTLOCK LOCK
OUT_SEL2
REF0
REF1
REF2
REF2_SYNC
REF_FAIL0
REF_FAIL1
REF_FAIL2
REF_SEL1:0
RST
Master Clock
MUX
TIE
Corrector
Circuit
Virtual
Reference
DPLL
E1
Synthesizer
Reference
Monitor
TIE
Corrector
Enable
State Machine
Mode
Control
Frequency
Select
MUX
DS1
Synthesizer
SDH
Synthesizer
Programmable
Synthesizer
IEEE
1149.1a
C2o
C4/C65o
C8/C32o
C16o
F4/F65o
F8/F32o
F16o
C1.5o
C3o
C19o
F2ko
C6/8.4/34/44o
OUT_SEL1:0
TRST
MODE_SEL1:0
HMS HOLDOVER SEC_MSTR APP_SEL1:0
TCK TDI TMS TDO
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2005, Zarlink Semiconductor Inc. All Rights Reserved.
1 page  
ZL30105
Data Sheet
List of Figures
Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3 - Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 4 - Behaviour of the Dis/Re-qualify Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5 - DS1 Out-of-Range Thresholds for APP_SEL1:0=00. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 6 - E1 Out-of-Range Thresholds for APP_SEL=01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7 - Out-of-Range Thresholds for APP_SEL=10 and APP_SEL=11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8 - REF2_SYNC Reference Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9 - Timing Diagram of Hitless Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10 - Timing Diagram of Hitless Mode Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11 - DPLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12 - Mode Switching in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13 - Reference Switching in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14 - Reference Selection in Automatic Mode (MODE_SEL=11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 15 - Mode Switching in Automatic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 16 - Automatic Reference Switching - Coarse Reference Failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 17 - Automatic Reference Switching - Out-of-Range Reference Failure . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 18 - Examples of REF2 & REF2_SYNC to Output Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 19 - Clock Redundancy with Two Independent Timing Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 20 - Clock Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 21 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 22 - Power-Up Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 23 - Typical Clocking Architecture of an ECTF H.110 System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 24 - Typical Clocking Architecture of a PICMG AdvancedTCA™ System . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 25 - Timing Parameter Measurement Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 26 - REF0/1/2 Input Timing and Input to Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 27 - REF2_SYNC Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 28 - E1 Output Timing Referenced to F8/F32o. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 29 - DS1 Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 30 - SDH Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 31 - DS3, E3, E2 and DS2 Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5
Zarlink Semiconductor Inc.
5 Page 
ZL30105
Data Sheet
Pin #
56
57
58
59
60
61
62
63
64
Name
Description
REF1
Reference (Input). See REF0 pin description.
REF2
Reference (Input). See REF0 pin description.
REF2_SYNC
REF2 Synchronization Frame Pulse (Input). This is the 2 kHz or 8 kHz (multi) frame
pulse synchronization input associated with the REF2 reference. While the PLL is locked
to the REF2 input reference the output (multi) frame pulses are synchronized to this input.
This pin is internally pulled down to GND.
SEC_MSTR
Secondary Master Mode Selection (Input). A logic low at this pin selects the Primary
Master mode of operation with 1.8 Hz or 3.6 Hz DPLL loop filter bandwidth. A logic high
selects Secondary Master mode which forces the PLL to clear its TIE corrector circuit and
lock to the selected reference using a high bandwidth loop filter and a phase slope
limiting of 9.5 ms/s.
APP_SEL0 Application Selection (Input). See APP_SEL1 pin description.
VDD Positive Supply Voltage. +3.3 VDC nominal
IC Internal Connection. Connect to GND.
TIE_CLR
TIE Circuit Reset (Input). A logic low at this input resets the Time Interval Error (TIE)
correction circuit resulting in a realignment of input phase with output phase.
FASTLOCK Fast Lock (Input). Set temporarily high to allow the ZL30105 to quickly lock to the input
reference (one second locking time).
3.0 Functional Description
The ZL30105 is an SDH/PDH Synchronizer for Redundant System Clocks, providing timing and synchronization
signals to interface circuits for the following types of primary rate digital transmission links, see Table 1:
• DS1 compliant with ANSI T1.403 and Telcordia GR-1244-CORE Stratum 4/4E
• E1 compliant with ITU-T G.703 and ETSI ETS 300 011
• PDH compliant with Telcordia GR-1244-CORE Stratum 3
• SDH compliant with ITU-T G.813 option 1 and Telcordia GR-253-CORE
Figure 1 is a functional block diagram of the ZL30105 which is described in the following sections.
3.1 Reference Select Multiplexer (MUX)
The ZL30105 accepts three simultaneous reference input signals and operates on their rising edges. One of them,
the primary reference (REF0), the secondary reference (REF1) or the tertiary reference (REF2) signal is selected
as input to the TIE Corrector Circuit based on the Reference Selection (REF_SEL1:0) inputs.
The use of the combined REF2 and REF2_SYNC inputs allows for a very accurate phase alignment of the output
frame pulses to the 2 kHz or 8 kHz (multi) frame pulse supplied to the REF2_SYNC input. This feature supports the
implementation of Primary and Secondary Master system clocks in AdvancedTCA or H.110 systems.
3.2 Reference Monitor
The input references are monitored by three independent reference monitor blocks, one for each reference. The
block diagram of a single reference monitor is shown in Figure 3. For each reference clock, the frequency is
detected and the clock is continuously monitored for three independent criteria that indicate abnormal behavior of
the reference signal, for example; long term drift from its nominal frequency or excessive jitter. To ensure proper
11
Zarlink Semiconductor Inc.
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ZL30105.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ZL30100 | T1/E1 System Synchronizer |  Zarlink Semiconductor Inc |
| ZL30101 | T1/E1 Stratum 3 System Synchronizer | Zarlink Semiconductor Inc |
| ZL30102 | T1/E1 Stratum 4/4E Redundant System Clock Synchronizer | Zarlink Semiconductor |
| ZL30105 | T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer | Zarlink Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |