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PDF K7Q163664B Data sheet ( Hoja de datos )

Número de pieza K7Q163664B
Descripción (K7Q161864B / K7Q163664B) 512Kx36 & 1Mx18 QDR TM b4 SRAM
Fabricantes Samsung semiconductor 
Logotipo Samsung semiconductor Logotipo



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K7Q163664B
K7Q161864B
Document Title
512Kx36-bit, 1Mx18-bit QDRTM SRAM
Revision History
Rev. No.
History
0.0 1. Initial document.
1.0 1. Final spec release
512Kx36 & 1Mx18 QDRTM b4 SRAM
Draft Date
Jan. 27, 2004
Mar. 18, 2004
Remark
Advance
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-
tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 - Mar. 2004
Rev 1.0

1 page




K7Q163664B pdf
K7Q163664B
K7Q161864B
512Kx36 & 1Mx18 QDRTM b4 SRAM
GENERAL DESCRIPTION
The K7Q163664B and K7Q161864B are 18,874,368-bits QDR(Quad Data Rate) Synchronous Pipelined Burst SRAMs.
They are organized as 524,288 words by 36bits for K7Q163654B and 1,048,576 words by 18 bits for K7Q161864B.
The QDR operation is possible by supporting DDR read and write operations through separate data output and input ports
with the same cycle. Memory bandwidth is maxmized as data can be transfered into sram
on every rising edge of K and K, and transfered out of sram on every rising edge of C and C.
And totally independent read and write ports eliminate the need for high speed bus turn around.
Address for read and write are latched on alternate rising edges of the input clock K.
Data inputs, and all control signals are synchronized to the input clock ( K or K ).
Normally data outputs are synchronized to output clocks ( C and C ), but when C and C are tied high,
the data outputs are synchronized to the input clocks ( K and K ).
Common address bus is used to access address both for read and write operations.
The internal burst counter is fiexd to 4-bit sequential for both read and write operations, reguiring tow full clock bus cycles.
Any request that attempts to interrupt a burst operation in progress is ignored.
Synchronous pipeline read and late write enable high speed operations.
Simple depth expansion is accomplished by using R and W for port selection.
Byte write operation is supported with BW0 and BW1 ( BW2 and BW3 ) pins.
IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoring package pads attachment status with system.
The K7Q163664B and K7Q161864B are implemented with SAMSUNG's high performance 6T CMOS technology and is available
in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
Read Operations
Read cycles are initiated by activating R at the rising edge of the positive input clock K.
Address is presented and stored in the read address register synchronized with K clock.
For 4-bit burst DDR operation, it will access four 36-bit or 18-bit data words with each read command.
The first pipelined data is transfered out of the device triggered by C clock following next K clock rising edge.
Next burst data is triggered by the rising edge of following C clock rising edge.
The process continues until all four data are transfered.
Continuous read operations are initiated with K clock rising edge.
And pipelined data are transferred out of device on every rising edge of both C and C clocks.
In case C and C tied to high, output data are triggered by K and K instead of C and C.
When the R is disabled after a read operation, the K7Q163664B and K7Q161864B will first complete burst read operation
before entering into deselect mode at the next K clock rising edge.
Then output drivers disabled automatically to high impedance state.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: VSS, VDD, VDDQ, VREF, then VIN. VDD and VDDQ can be applied
simultaneously, as long as VDDQ does not exceed VDD by more than 0.5V during power-up. The following power-down supply voltage
removal sequence is recommended: VIN, VREF, VDDQ, VDD, VSS. VDD and VDDQ can be removed simultaneously, as long as VDDQ
does not exceed VDD by more than 0.5V during power-down.
- 5 - Mar. 2004
Rev 1.0

5 Page





K7Q163664B arduino
K7Q163664B
K7Q161864B
512Kx36 & 1Mx18 QDRTM b4 SRAM
AC TEST CONDITIONS
Parameter
Symbol Value Unit
Core Power Supply Voltage
VDD 1.7~2.6 V
Output Power Supply Voltage
VDDQ 1.4~1.9 V
Input High/Low Level
VIH/VIL 1.25/0.25 V
Input Reference Level
VREF
0.75
V
Input Rise/Fall Time
TR/TF 0.3/0.3 ns
Output Timing Reference Level
VDDQ/2
V
Note: Parameters are tested with RQ=250
AC TEST OUTPUT LOAD
VREF 0.75V
VDDQ/2
SRAM
Zo=50
50
250
ZQ
PIN CAPACITANCE
PRMETER
SYMBOL
Address Control Input Capacitance
CIN
Input and Output Capacitance
COUT
Clock Capacitance
CCLK
Note: 1. Parameters are tested with RQ=250and VDDQ=1.5V.
2. Periodically sampled and not 100% tested.
TESTCONDITION
VIN=0V
VOUT=0V
-
TYP
4
6
5
MAX
5
7
6
Unit NOTES
pF
pF
pF
APPLICATION INFORMATION
1Mx18
SRAM#1
SRAM#4
R=250
R=250
Vt D0-17
ZQ
Q0-17
R SA R W BW0 BW1 C C K K
ZQ
D0-17
Q0-17
SA RW BW0 BW1 C C K K
Data In
Data Out
Address
R
W
BW0-7
MEMORY
CONTROLLER
Return CLK
Source CLK
Return CLK
Source CLK
Vt
Vt
R=50Vt=VREF
Vt
Vt
R
- 11 -
Mar. 2004
Rev 1.0

11 Page







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