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PDF MAX1448 Data sheet ( Hoja de datos )
| Número de pieza | MAX1448 | |
| Descripción | Low-Power ADC | |
| Fabricantes | Maxim Integrated Products | |
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19-5400; Rev 2; 5/04
EVAALVUAAILTAIOBNLEKIT
10-Bit, 80Msps, Single 3.0V, Low-Power
ADC with Internal Reference
General Description
The MAX1448 3V, 10-bit analog-to-digital converter
(ADC) features a fully differential input, a pipelined 10-
stage ADC architecture with wideband track-and-hold
(T/H), and digital error correction incorporating a fully
differential signal path. The ADC is optimized for low-
power, high dynamic performance in imaging and digi-
tal communications applications. The converter
operates from a single 2.7V to 3.6V supply, consuming
only 120mW while delivering a 59dB (typ) signal-to-
noise ratio (SNR) at a 20MHz input frequency. The fully
differential input stage has a -3dB 400MHz bandwidth
and may be operated with single-ended inputs. In addi-
tion to low operating power, the MAX1448 features a
5µA power-down mode for idle periods.
An internal 2.048V precision bandgap reference is
used to set the ADC full-scale range. A flexible refer-
ence structure allows the user to supply a buffered,
direct, or externally derived reference for applications
requiring increased accuracy or a different input volt-
age range.
Lower speed, pin-compatible versions of the MAX1448
are also available. Refer to the MAX1444 data sheet for
a 40Msps version and to the MAX1446 data sheet for a
60Msps version.
The MAX1448 has parallel, offset binary, CMOS-com-
patible three-state outputs that can be operated from
1.7V to 3.6V to allow flexible interfacing. The device is
available in a 5mm x 5mm 32-pin TQFP package and is
specified over the extended industrial (-40°C to +85°C)
temperature range.
Features
o Single 3.0V Operation
o Excellent Dynamic Performance
59dB SNR at fIN = 20MHz
74dBc SFDR at fIN = 20MHz
o Low Power
40mA (Normal Operation)
5µA (Shutdown Mode)
o Fully Differential Analog Input
o Wide 2VP-P Differential Input Voltage Range
o 400MHz -3dB Input Bandwidth
o On-Chip 2.048V Precision Bandgap Reference
o CMOS-Compatible Three-State Outputs
o 32-Pin TQFP Package
o Evaluation Kit Available (MAX1448 EV Kit)
PART
MAX1448EHJ
Ordering Information
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
32 TQFP
Functional Diagram
________________________Applications
Ultrasound Imaging
CCD Imaging
Baseband and IF Digitization
Digital Set-Top Boxes
Video Digitizing Applications
CLK
IN+
T/H
IN-
PD REF
CONTROL
PIPELINEADC
REFSYSTEM+
BIAS
MAX1448
VDD
GND
D
E
C
10
OUTPUT
DRIVERS
D9–D0
OVDD
OGND
REFOUT REFIN REFP COM REFN
OE
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
10-Bit, 80Msps, Single 3.0V, Low-Power
ADC with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.0V, OVDD = 2V, 0.1µF and 1µF capacitors from REFP, REFN, and COM to GND, VREFIN = 2.048V, REFOUT connected to
REFIN through a 10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs, fCLK = 83.3MHz, TA = TMIN
to TMAX, unless otherwise noted. ≥ +25°C guaranteed by production test, < +25°C guaranteed by design and characterization; typical
values are at TA = +25°C.)
PARAMETER
DIGITAL OUTPUTS (D9–D0)
Output Voltage Low
SYMBOL
CONDITIONS
VOL ISINK = 200µA
Output Voltage High
VOH
ISOURCE = 200µA
Three-State Leakage Current
ILEAK
OE = OVDD
Three-State Output Capacitance COUT OE = OVDD
MIN TYP MAX UNITS
OVDD -
0.2
5
0.2 V
V
±10 µA
pF
POWER REQUIREMENTS
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
Output Supply Current
Power-Supply Rejection
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
OE Fall to Output Enable
OE Rise to Output Disable
CLK Pulse Width High
CLK Pulse Width Low
Wake-Up Time
VDD
OVDD
IVDD
IOVDD
PSRR
Operating, fIN = 20MHz at -0.5dB FS
Shutdown, clock idle, PD = OE = OVDD
Operating, CL = 15pF, fIN = 20MHz at
-0.5dB FS
Shutdown, clock idle, PD = OE = OVDD
Offset
Gain
tDO
tENABLE
tDISABLE
tCH
tCL
tWAKE
Figure 6 (Note 3)
Figure 5
Figure 5
Figure 6, clock period 12ns
Figure 6, clock period 12ns
(Note 4)
2.7 3.0 3.6
V
1.7 3.0 3.6
V
40 47 mA
4 15 µA
8 mA
1 20 µA
±0.2 mV/V
±0.1 %/V
58
10
15
6±1
6±1
1.5
ns
ns
ns
ns
ns
µs
Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dB FS referenced to a 1.024V full-scale
input voltage range.
Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB better if referenced to the two-tone envelope.
Note 3: Digital outputs settle to VIH,VIL.
Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
_______________________________________________________________________________________ 5
5 Page 
10-Bit, 80Msps, Single 3.0V, Low-Power
ADC with Internal Reference
_______________Detailed Description
The MAX1448 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Each sample moves through a pipeline stage
every half clock-cycle. Counting the delay through the
output latch, the clock-cycle latency is 5.5.
A 1.5-bit (2-comparator) flash ADC converts the held
input voltage into a digital code. The following digital-
to-analog converter (DAC) converts the digitized result
back into an analog voltage, which is then subtracted
from the original held input signal. The resulting error
signal is then multiplied by two, and the product is
passed along to the next pipeline stage where the
process is repeated. Each stage provides a 1-bit reso-
lution. Digital error correction compensates for ADC
comparator offsets in each pipeline stage and ensures
no missing codes.
Input Track-and-Hold Circuit
Figure 2 displays a simplified functional diagram of the
input track-and-hold (T/H) circuit in both track and hold
mode. In track mode, switches S1, S2a, S2b, S4a, S4b,
S5a, and S5b are closed. The fully differential circuit
samples the input signal onto the two capacitors (C2a
and C2b) through S4a and S4b. S2a and S2b set the
common mode for the amplifier input and open simulta-
MDAC
VIN T/H Σ x2 VOUT
FLASH
ADC
DAC
1.5 BITS
neously with S1, sampling the input waveform. S4a and
S4b are then opened before S3a and S3b connect
capacitors C1a and C1b to the amplifier output, and
S4c is closed. The resulting differential voltage is held
on C2a and C2b. The amplifier is used to charge C1a
and C1b to the same values originally held on C2a and
C2b. This value is then presented to the first-stage
quantizer and isolates the pipeline from the fast-chang-
ing input. The wide-input-bandwidth T/H amplifier
allows the MAX1448 to track and sample/hold analog
inputs of high frequencies beyond Nyquist. Analog
inputs (IN+ and IN-) can be driven either differentially
or single-ended. It is recommended to match the
impedance of IN+ and IN- and set the common-mode
voltage to midsupply (VDD/2) for optimum performance.
Analog Input and Reference Configuration
The MAX1448 full-scale range is determined by the
internally generated voltage difference between REFP
(VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The
ADC’s full-scale range is user-adjustable through the
REFIN pin, which provides a high input impedance for
this purpose. REFOUT, REFP, COM (VDD/2), and REFN
are internally buffered, low-impedance outputs.
INTERNAL
BIAS
S2a
COM
S5a
C1a S3a
S4a
IN+
C2a
S4c S1
IN-
S4b
C2b
C1b
OUT
OUT
VIN STAGE 1
STAGE 2
STAGE 10
DIGITAL CORRECTION LOGIC
10
D9–D0
VIN = INPUT VOLTAGE BETWEEN
IN+ AND IN- (DIFFERENTIAL OR SINGLE ENDED)
S3b
S2b S5b
INTERNAL
BIAS
COM
TRACK TRACK
CLK
HOLD
HOLD
INTERNAL
NON OVERLAPPING
CLOCK SIGNALS
Figure 1. Pipelined Architecture—Stage Blocks
Figure 2. Internal Track-and-Hold Circuit
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet MAX1448.PDF ] | |
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