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PDF ICX282AK Data sheet ( Hoja de datos )
| Número de pieza | ICX282AK | |
| Descripción | Diagonal 11mm (Type 2/3) Frame Readout CCD Image Sensor | |
| Fabricantes | Sony Corporation | |
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ICX282AK
Diagonal 11mm (Type 2/3) Frame Readout CCD Image Sensor with Square Pixel for Color Cameras
Description
The ICX282AK is a diagonal 11mm (Type 2/3)
interline CCD solid-state image sensor with a square
pixel array and 5.07M effective pixels. Frame readout
allows all pixels' signals to be output independently
within approximately 1/3.75 second. In addition, output
is possible using various addition and pulse elimination
methods. This chip features an electronic shutter with
variable charge-storage time. Adoption of a design
specially suited for frame readout ensures a saturation
signal level equivalent to that when using field readout.
High resolution and high color reproductively are
achieved through the use of Ye, Cy, Mg and G
complementary color mosaic filters as the color filters.
Further, high sensitivity and low dark current are
achieved through the adoption of Super HAD CCD
technology.
This chip is suitable for applications such as
electronic still cameras, PC input cameras, etc.
24 pin DIP (Plastic)
Features
• High horizontal and vertical resolution
• Supports 10 types of readout modes
Frame readout mode, 2× speed mode (1), 2× speed mode (2), 8× speed mode,
center scan mode (1), center scan mode (2), center scan mode (3),
center scan mode (4), AF mode (1), AF mode (2)
• Square pixel
• Horizontal drive frequency: 22.5MHz
• No voltage adjustments (reset gate and substrate bias are not adjusted.)
• Ye, Cy, Mg and G complementary color mosaic filters on chip
• High sensitivity, low dark current, excellent anti-blooming characteristics
• Continuous variable-speed shutter
• Horizontal register, reset gate: 3.3V drive
V
• 24-pin high-precision plastic package
Pin 1
Device Structure
• Interline CCD image sensor
• Image size:
Diagonal 11mm (Type 2/3)
12
Pin 13
H
58
• Total number of pixels: 2658 (H) × 1970 (V) approx. 5.24M pixels
• Number of effective pixels: 2588 (H) × 1960 (V) approx. 5.07M pixels
• Number of active pixels: 2580 (H) × 1944 (V) approx. 5.02M pixels
• Number of recommended recording pixels:
Optical black position
(Top View)
2560 (H) × 1920 (V) approx. 4.92M pixels
• Chip size:
9.74mm (H) × 7.96mm (V)
• Unit cell size:
3.4µm (H) × 3.4µm (V)
• Optical black:
Horizontal (H) direction: Front 12 pixels, rear 58 pixels
Vertical (V) direction: Front 8 pixels, rear 2 pixels
• Number of dummy bits: Horizontal 28
Vertical 1 (even fields only)
• Substrate material:
Silicon
2
8
∗ Super HAD CCD is a registered trademark of Sony Corporation. Super HAD CCD is a CCD that drastically improves sensitivity by introducing
newly developed semiconductor technology by Sony Corporation into Sony's high-performance HAD (Hole-Accumulation Diode) sensor.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01626A31-PS
1 page  
ICX282AK
Clock Equivalent Circuit Constant
Item Symbol
Capacitance between vertical transfer clock
and GND
CφV1γ, CφV3γ
CφV1B, CφV3B
CφV2, CφV4
CφV1γ 2, CφV3γ4
CφV1B2, CφV3B4
CφV23γ, CφV41γ
CφV23B, CφV41B
Capacitance between vertical transfer clocks
CφV1γ 3γ
CφV1B3B
CφV1γ 3B, CφV1B3γ
CφV24
CφV1γ1B, CφV3γ 3B
Capacitance between horizontal transfer clock
and GND
CφH1
CφH2
Capacitance between horizontal transfer clocks CφHH
Capacitance between reset gate clock and GND CφRG
Capacitance between substrate clock and GND CφSUB
Vertical transfer clock series resistor
R1γ, R3γ
R1B, R2, R3B, R4
Vertical transfer clock ground resistor
RGND
Horizontal transfer clock series resistor
RφH
Min.
Typ.
1800
6800
5600
560
680
180
270
56
330
91
120
100
82
62
110
5
1500
62
43
16
7.5
Max. Unit Remarks
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Ω
Ω
Ω
Ω
Note 1) γ = A, C for each vertical transfer clock capacitance.
Note 2) The relationships of V1A = V1C and V3A = V3C are established for each vertical transfer clock
capacitance.
Note 3) CφV1A1C and CφV3A3C are sufficiently small relative to other capacitance between vertical transfer
clocks, and are also below the measurement limit, so these are omitted from the equivalent circuit
diagrams and the above table.
Vφ2
Vφ1γ (γ = A, C)
R1γ
CφV24
CφV1γ 2
R2
CφV1γ 3γ
CφV23γ
Vφ3γ (γ = A, C)
R3γ
CφV1B2
CφV1γ
CφV1γ 1B
CφV1B3γ
CφV1B
CφV4
CφV41γ
CφV23B
CφV2
CφV3γ
CφV3γ 3B
CφV3B CφV1γ 3B
CφV3γ 4
Vφ1B R1B
CφV41B
RGND
CφV3B4
CφV1B3B
R4
R3B Vφ3B
Hφ1A
Hφ1B
RφH
RφH
CφH1
CφHH
RφH
Hφ2A
RφH
Hφ2B
CφH2
Vφ4
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
–5–
5 Page 
ICX282AK
Readout modes list
The readout method, frame rate, number of output lines and other information for each readout mode are
shown in the table below.
Mode
Readout
method
High-speed
sweep for
preventing smear
Addition
method
Frame
readout
Frame
readout
Yes
None
2× speed (1) 2/4 lines
Yes
None
2× speed (2)
Frame
readout
Yes
Vertical
2 lines
8× speed 4/16 lines
None
Vertical
2 lines
Center scan
(1)
2/4 lines
None
None
Center scan
(2)
2/4 lines
None
None
Center scan Frame
(3) readout
Yes
None
Center scan Frame
(4) readout
Yes
None
AF (1)
4/16 lines
None
Vertical
2 lines
AF (2)
4/16 lines
None
Vertical
2 lines
Frame rate [frame/s]
NTSC
PAL
3.75 3.57
7.49 7.14
6.66 6.25
29.97
25
14.985
12.5
26.35
7.02
11.988
10
59.94
50
119.88
100
Number of output
effective image data
lines
1960
980
980
245
NTSC: 484, PAL: 587
246
968
NTSC: 492, PAL: 620
NTSC: 104, PAL: 128
NTSC: 34, PAL: 46
– 11 –
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ICX282AK.PDF ] | |
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