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PDF M41T93 Data sheet ( Hoja de datos )
| Número de pieza | M41T93 | |
| Descripción | Serial SPI bus RTC | |
| Fabricantes | ST Microelectronics | |
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M41T93
Serial SPI bus RTC with battery switchover
Preliminary Data
Feature summary
■ 2.0 to 5.5V clock operating voltage
■ Ultra-low battery supply current of 365nA
■ Counters for tenths/hundredths of seconds,
seconds, minutes, hours, day, date, month,
year, and century
■ Programmable clock calibration (analog and
digital)
■ Automatic switch-over and reset output
circuitry (fixed reference)
– M41T93S: VCC = 3.0V to 5.5V
(2.85V ≤VRST ≤3.00V)
– M41T93R: VCC = 2.7V to 5.5V
(2.55V ≤VRST ≤2.70V)
– M41T93Z: VCC = 2.38V to 5.50V
(2.25V ≤VRST ≤2.38V)
■ Compatible with SPI Bus serial interface
(positive clock SPI modes)
■ Programmable alarm with interrupt function
(valid even during battery back-up mode)
■ Optional 2nd programmable alarm available
■ Square wave output (defaults to 32kHz on
power-up)
■ RESET (RST) output
■ Watchdog timer
■ Programmable 8-bit counter/timer
■ 7 Bytes of battery-backed user SRAM
■ Battery low flag
■ Power-down time stamp (HT Bit)
■ Low operating current of 80µA
■ Oscillator stop detection
■ Battery or super-cap™ Back-up
■ Operating temperature of –40°C to 85°C
QFN16, 4mm x 4mm (QA)
18
1
SOX18 (MY, 18-pin, 300mil SOIC
with Embedded Crystal)
■ Package options include:
– a 16-Lead QFN or an 18-Lead Embedded
Crystal SOIC
■ RoHS Compliance: lead-free components are
compliant with the RoHS directive.
August 2006
Rev 1
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/49
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49
1 page  
M41T93
List of Tables
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Signal name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Function table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock/control register map (32 Bytes). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Digital calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Analog calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Alarm repeat modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Timer control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Interrupt operation (Bit TI/TP = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Timer source clock frequency selection (244.1µs to 4.25 hrs) . . . . . . . . . . . . . . . . . . . . . . 30
Timer countdown value register bits (addr 11h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Square wave output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Century bits examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Initial power-on default values (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Initial power-up default values (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Crystal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
QFN16 – 16-lead, Quad, Flat Package, No Lead, 4x4mm body, Mech. Data . . . . . . . . . . 44
SOX18 – 18-lead Plastic SO, 300mils, embedded crystal, pkg. mech. data . . . . . . . . . . . 46
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5/49
5 Page 
M41T93
Summary description
1.1
1.1.1
1.1.2
1.1.3
1.1.4
SPI signal description
Serial data output (SDO)
The output pin is used to transfer data serially out of the Memory. Data is shifted out on the
falling edge of the serial clock.
Serial data input (SDI)
The input pin is used to transfer data serially into the device. Instructions, addresses, and
the data to be written, are each received this way. Input is latched on the rising edge of the
serial clock.
Serial clock (SCL)
The serial clock provides the timing for the serial interface (as shown in Figure 18 on
page 40 and Figure 19 on page 40). The W/R Bit, addresses, or data are latched, from the
input pin, on the rising edge of the clock input. The output data on the SDO pin changes
state after the falling edge of the clock input.
The M41T93 can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
(CPOL, CPHA) = ('0', '0'), or
(CPOL, CPHA) = ('1', '1').
For these two modes, input data (SDI) is latched in by the low-to-high transition of clock
SCL, and output data (SDO) is shifted out on the high-to-low transition of SCL (see Table 2
on page 10 and <Blue>Figure 6., page 10).
Chip enable (E)
When E is high, the memory device is deselected, and the SDO output pin is held in its high
impedance state.
After power-on, a high-to-low transition on E is required prior to the start of any operation.
11/49
11 Page | ||
| Páginas | Total 49 Páginas | |
| PDF Descargar | [ Datasheet M41T93.PDF ] | |
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