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PDF K4M64163PH Data sheet ( Hoja de datos )
| Número de pieza | K4M64163PH | |
| Descripción | 1M x 16Bit x 4 Banks Mobile SDRAM | |
| Fabricantes | Samsung semiconductor | |
| Logotipo |  |
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K4M64163PH - R(B)G/F
Mobile-SDRAM
1M x 16Bit x 4 Banks Mobile SDRAM in 54CSP
FEATURES
GENERAL DESCRIPTION
• 1.8V power supply.
The K4M64163PH is 67,108,864 bits synchronous high data
• LVCMOS compatible with multiplexed address.
rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits,
• Four banks operation.
fabricated with SAMSUNG′s high performance CMOS technol-
• MRS cycle with address key programs.
ogy. Synchronous design allows precise cycle control with the
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page).
-. Burst type (Sequential & Interleave).
• EMRS cycle with address key programs.
• All inputs are sampled at the positive going edge of the system
clock.
use of system clock, and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth and high per-
formance memory system applications.
• Burst read single-bit write operation.
• Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
-. DS (Driver Strength)
• DQM for masking.
• Auto refresh.
• 64ms refresh period (4K cycle).
• Commercial Temperature Operation (-25°C ~ 70°C).
• Extended Temperature Operation (-25°C ~ 85°C).
• 54Balls CSP with 0.8mm ball pitch( -RXXX -Pb, -BXXX -Pb Free).
ORDERING INFORMATION
Part No.
K4M64163PH-R(B)G/F75
Max Freq.
133MHz(CL3), 83MHz(CL2)
K4M64163PH-R(B)G/F90
111MHz(CL3), 83MHz(CL2)
K4M64163PH-R(B)G/F1L
111MHz(CL=3)*1, 66MHz(CL2)
- R(B)G : Low Power, Extended Temperature(-25°C ~ 85°C)
- R(B)F : Low Power, Commercial Temperature(-25°C ~ 70°C)
Interface
LVCMOS
Package
54 CSP Pb
(Pb Free)
Notes :
1. In case of 40MHz Frequency, CL1 can be supported.
2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is
potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of a product
contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
1 December 2003
1 page  
K4M64163PH - R(B)G/F
Mobile-SDRAM
DC CHARACTERISTICS
Recommended operating conditions(Voltage referenced to VSS = 0V, TA = -25°C ~ 85°C for Extended, -25°C ~ 70°C for Commerial)
Parameter
Symbol
Test Condition
Version
-75 -90 -IL
Unit Note
Operating Current
(One Bank Active)
Burst length = 1
ICC1 tRC ≥ tRC(min)
IO = 0 mA
25 25 25 mA 1
Precharge Standby Current in ICC2P CKE ≤ VIL(max), tCC = 10ns
power-down mode
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞
Precharge Standby Current
in non power-down mode
ICC2N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC2NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
0.3
0.3
6.5
1
mA
mA
Active Standby Current
in power-down mode
Active Standby Current
in non power-down mode
(One Bank Active)
ICC3P CKE ≤ VIL(max), tCC = 10ns
ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞
ICC3N
CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns
Input signals are changed one time during 20ns
ICC3NS
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
5
1
12
1
mA
mA
mA
Operating Current
(Burst Mode)
ICC4
IO = 0 mA
Page burst
4Banks Activated
tCCD = 2CLKs
60 50 50 mA 1
Refresh Current
ICC5 tARFC ≥ tARFC(min)
50 50 50 mA 2
Internal TCSR Max 40
Max 85 °C
Self Refresh Current
ICC6 CKE ≤ 0.2V
Full Array
1/2 of Full Array
90
80
180
160 uA
1/4 of Full Array
75
150
NOTES:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).
5 December 2003
5 Page 
K4M64163PH - R(B)G/F
Mobile-SDRAM
Partial Array Self Refresh
1. In order to save power consumption, Mobile SDRAM has PASR option.
2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode : Full Array, 1/2 of Full Array and 1/4 of Full Array.
BA1=0 BA1=0
BA0=0 BA0=1
BA1=0 BA1=0
BA0=0 BA0=1
BA1=0 BA1=0
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
BA1=1 BA1=1
BA0=0 BA0=1
- Full Array
- 1/2 Array
- 1/4 Array
Partial Self Refresh Area
Internal Temperature Compensated Self Refresh (TCSR)
Note :
1. In order to save power consumption, Mobile-SDRAM includes the internal temperature sensor and control units to control the
self refresh cycle automatically according to the two temperature range ; Max. 40 °C, Max. 85 °C.
2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.
Temperature Range
Max. 40 °C
Max. 85 °C
Full Array
90
180
Self Refresh Current (Icc 6)
1/2 of Full Array
80
160
1/4 of Full Array
75
150
Unit
uA
B. POWER UP SEQUENCE
1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.
- Apply VDD before or at the same time as VDDQ.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS.
EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used.
The default state without EMRS command issued is the half driver strength and full array refreshed.
The device is now ready for the operation selected by EMRS.
For operating with DS or PASR , set DS or PASR mode in EMRS setting stage.
In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not
needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.
11 December 2003
11 Page | ||
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