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PDF A8286 Data sheet ( Hoja de datos )

Número de pieza A8286
Descripción Dual LNB Supply and Control Voltage Regulator
Fabricantes Allegro MicroSystems 
Logotipo Allegro MicroSystems Logotipo



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A8286
Dual LNB Supply and Control Voltage Regulator
Features and Benefits
2-wire serial I2C™ -compatible interface: control (write)
and status (read)
LNB voltages (16 programmable levels) compatible with
all common standards
Tracking switch-mode power converter for lowest dissipation
Integrated converter switches and current sensing
Provides up to 650 mA per channel and 1.0 A total
continuous load current
Provides up to 700 mA per channel and 1.1 A total for 2000 ms
Output current limit of 900 mA typical, with 48 ms timer
Static current limit circuit allows full current at startup and
1318V output transition; reliably starts wide load range
Push-pull output stage minimizes 1318V and 1813V
output transition times for highly capacitive loads
Adjustable rise/fall time via external timing capacitor
Built-in tone oscillator, factory-trimmed to 22 kHz
facilitates DiSEqC™ tone encoding, even at no-load
Four methods of 22 kHz tone generation, via I2C™ data
bits and/or external pin
22 kHz tone detector facilitates DiSEqC™ 2.0 decoding
Auxiliary modulation input
LNB overcurrent with timer
Provides VOUT within 19 to 21 VDC at 700 mA for
SWM (single wire multiswitch) operation
Diagnostics for output voltage level, input supply UVLO,
and DiSEqC™ tone output
Cable disconnect diagnostic
Package:
28 pin 5 mm × 5mm
QFN/MLP (suffix ET)
Description
Intended for analog and digital satellite receivers, this dual
low-noise block converter regulator (LNBR) is a monolithic
linear and switching voltage regulator, specifically designed to
provide the power and the interface signals to two LNB down
converters via coaxial cables. TheA8286 requires few external
components, with the boost switches and compensation circuitry
integrated inside of the device. A high switching frequency is
chosen to minimize the size of the passive filtering components,
further assisting in cost reduction. The high level of component
integration ensures extremely low noise and ripple figures.
The A8286 has been designed for high efficiency, utilizing
the Allegro® advanced BCD process. The integrated boost
switches have been optimized to minimize both switching and
static losses. To further enhance efficiency, the voltage drop
across the tracking regulators has been minimized.
The A8286 has integrated tone detection capability, to support
full two-way DiSEqC™ communications. Several schemes
are available for generating tone signals, all the way down
to no-load, and using either the internal clock or an external
time source.
Continued on the next page…
VS
VDD
A Channel 1 of 2 channels shown.
B R8-C11 network is needed only when high
inductive load is applied, such as ProBrand LNB.
C D3 and D4 are used for surge protection.
D Either C12 or C9 should be used, but not both.
Functional Block Diagram
C2
100 MF
A
Channel 1 L1
33 MH
L3
D1 1 MH
A8286
C5
100 MF
C6
1 MF
R4 R5
C4
100 nF
TDO1 EXTM1
LX1 GNDLX1
BOOST1 VCP1
VIN
C1
100 nF
VREG
C3
220 nF
Regulator
R3
R2
R1
SDA
SCL
I2 C
Compatible
Interface
IRQ
Boost
Converter
Charge
Pump
C12 D
TMode1
EXTM1
Fsw
DAC
LNB
Voltage
Control
Wave
Shape
TCAP1
TGate1
Fault Monitor
OCP1
OCP2
PNG1
PNG2
TSD
VUV
Fsw
Clock
Divider 22 kHz
Oscillator
PAD
GND
VPump
Linear
Stage
TDO1
Tone
Detect
R6
157
LNB1
C8
D2 220 nF
L2
220 MH
R8
30 7
C9
220 nF
D
TCAP1
C7
10 nF
C11
0.68 MF
B
TDI1
R7
100 7
C10
10 nF
D3
C
VOUT1
C13
10 nF
D4
C
8286-DS, Rev. 3

1 page




A8286 pdf
A8286
Dual LNB Supply and Control Voltage Regulator
ELECTRICAL CHARACTERISTICS (continued) at TA = 25°C, VIN = 8 to 16 V, unless noted otherwise1
Characteristics
Symbol
Test Conditions
Min.
Tone
Tone Frequency
Tone Amplitude, Peak-to-Peak
Tone Duty Cycle
Tone Rise Time
Tone Fall Time
EXTM Logic Input
EXTM Input Leakage
Tone Detector
fTONE
VTONE(pp)
DCTONE
trTONE
tfTONE
VEXTM(H)
VEXTM(L)
IEXTMLKG
ILOAD = 0 to 500 mA, CLOAD = 750 nF
ILOAD = 0 to 500 mA, CLOAD = 750 nF
ILOAD = 0 to 500 mA, CLOAD = 750 nF
ILOAD = 0 to 500 mA, CLOAD = 750 nF
20
400
40
5
5
2.0
–1
Tone Detect Input Amplitude Receive, Peak-to-
Peak
VTDR(pp) fTONE = 22 kHz sine wave, TMODE = 0
300
Tone Detect Input Amplitude Transmit, Peak-
to-Peak
VTDT(pp)Int
VTDT(pp)Ext
fTONE = 22 kHz sine wave, using internal tone
(options 1 and 2, in figure 2)
fTONE = 22 kHz sine wave, using external
tone (options 3 and 4, in figure 2)
400
300
Tone Reject Input Amplitude, Peak-to-Peak
Frequency Capture
Input Impedance2
TDO Output Voltage
TDO Output Leakage
I2C™-Compatible Interface
VTRI(pp)
fTDI
ZTDI
VTDO(L)
ITDOLKG
fTONE = 22 kHz sine wave
600 mVpp sine wave
Tone present, ILOAD = 3 mA
Tone absent, VTDO = 7 V
17.6
Logic Input (SDA,SCL) Low Level
Logic Input (SDA,SCL) High Level
Logic Input Hysteresis
Logic Input Current
Logic Output Voltage SDA and IRQ
Logic Output Leakage SDA and IRQ
SCL Clock Frequency
Output Fall Time
Bus Free Time Between Stop/Start
Hold Time Start Condition
Setup Time for Start Condition
SCL Low Time
SCL High Time
Data Setup Time
Data Hold Time
Setup Time for Stop Condition
VSCL(L)
VSCL(H)
VI2CIHYS
II2CI
Vt2COut(L)
Vt2CLKG
fCLK
tfI2COut
tBUF
tHD:STA
tSU:STA
tLOW
tHIGH
tSU:DAT
tHD:DAT
tSU:STO
VI2CI = 0 to 7 V
ILOAD = 3 mA
Vt2COut = 0 to 7 V
Vt2COut(H) to Vt2COut(L)
2.0
–10
1.3
0.6
0.6
1.3
0.6
100
0
0.6
Typ. Max. Units
22 24 kHz
620 800 mV
50 60 %
10 15 μs
10 15 μs
––V
– 0.8 V
– 1 μA
– – mV
– – mV
– – mV
– 100 mV
– 26.4 kHz
8.6 – kΩ
– 0.4 V
– 10 μA
150
<±1.0
0.8
10
0.4
10
400
250
900
V
V
mV
μA
V
μA
kHz
ns
μs
μs
μs
μs
μs
ns
ns
μs
Continued on the next page…
Allegro MicroSystems, Inc.
5
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

5 Page





A8286 arduino
A8286
Dual LNB Supply and Control Voltage Regulator
Interrupt Request
The A8286 also provides an interrupt request pin, IRQ, which
is an open-drain, active-low output. This output may be connected
to a common IRQ line with a suitable external pull-up and can
be used with other I2C™-compatible devices to request attention
from the master controller.
The IRQ output becomes active when either the A8286 first
recognizes a fault condition, or at power-on, when the main sup-
ply, VIN , and the internal logic supply, VREG , reach the correct
operating conditions. It is only reset to inactive when the I2C™
master addresses the A8286 with the Read/Write bit set (causing a
read). Fault conditions are indicated by the TSD, VUV, and OCP
bits (when ODT is set to 1) and are latched in the Status register.
See the Status register section for full description.
The OCP (with ODT= 0), DIS, PNG, CAD and TDET status
bits do not cause an interrupt. All these bits are continually up-
dated, apart from the DIS bit, which changes when the LNB is
either disabled, intentionally or due to a fault, or is enabled.
When the master recognizes an interrupt, it addresses all slaves
connected to the interrupt line in sequence, and then reads the
status register to determine which device is requesting attention.
The A8286 latches all conditions in the Status register until the
completion of the data read. The action at the resampling point is
further defined in the Status Register section. The bits in the Sta-
tus register are defined such that the all-zero condition indicates
that the A8286 is fully active with no fault conditions.
When VIN is initially applied, the I2C™-compatible interface
does not respond to any requests until the internal logic supply
VREG has reached its operating level. Once VREG has reached this
point, the IRQ output goes active, and the VUV bit is set. After the
A8286 acknowledges the address, the IRQ flag is reset. After the
master reads the status registers, the registers are updated with the
VUV reset.
SDA
SCL
IRQ
Start
Address
R
Status Register 1
Stop
0 0 0 1 0 A1 A0 1 AK D7 D6 D5 D4 D3 D2 D1 D0 NAK
123456789
Fault
Event Read after Interrupt
Figure 4. I2C™ Interface. Read sequences after interrupt request.
Reload
Status Register
Allegro MicroSystems, Inc.
11
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com

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