PDF EP520 Data sheet ( Hoja de datos )

Número de pieza	EP520
Descripción	SDRAM Controller
Fabricantes	Eureka
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No Preview Available ! www.DataSheet4U.com EP520 SDRAM Controller December 5, 2000 Product Specification Eureka Technology, Inc. 4962 El Camino Real, Suite 108 Los Altos, CA 94022 USA Phone: +1 650-960-3800 Fax: +1 650-960-3805 E-Mail: [email protected] URL: www.eurekatech.com Features • Supports Virtex™, Virtex™-E, and Spartan™-II FPGAs • Supports industry standard SDRAM and PC100 SDRAM DIMM. • Supports register mode and non-register mode PC100 SDRAM DIMM. • Programmable memory size and data width. • Supports industrial standard 16Mbit, 64Mbit, 128Mbit and 256Mbit SDRAMs. • Supports burst size of 1 to 8 and full page burst. • Supports zero wait state burst data transfer to maximize data bandwidth. • Programmable SDRAM access timing parameters. • Automatic refresh generation with programmable refresh intervals. • Optional Error Correction Code (ECC). • Multiple external SDRAM partitions. • Supports external data buffer between user device and SDRAM data bus AllianceCORE™ Facts Core Speciﬁcs Supported Family Virtex Device Tested V50-6 CLB Slices 287 Clock IOBs1 1 IOBs1 116 Performance (MHz) 91 Xilinx Tools 3.2i Special Features None Provided with Core Documentation User guide Design File Formats EDIF netlist Constraints File Top520.ucf Verification VHDL or Verilog test bench Instantiation Templates VHDL, Verilog Reference designs & None application notes Additional Items None Simulation Tool Used Model Technology Modelsim™ 5.4b Support Support provided by Eureka Technology Notes: 1. Assuming all core I/Os are routed off-chip Applications • Networking equipment • Communication equipment • Video systems • Image processing equipment • Medical equipment • Avionics • PC peripherals December 5, 2000 3-1 1 page

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Número de pieza	Descripción	Fabricantes
EP520	SDRAM Controller	Eureka

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