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PDF 25LC320A Data sheet ( Hoja de datos )
| Número de pieza | 25LC320A | |
| Descripción | 32K SPI Bus Serial EEPROM | |
| Fabricantes | Microchip Technology | |
| Logotipo |  |
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25AA320A/25LC320A
32K SPI Bus Serial EEPROM
Device Selection Table
Part Number
VCC Range
25LC320A
25AA320A
2.5-5.5V
1.8-5.5V
Page Size
32 Byte
32 Byte
Temp. Ranges
I,E
I
Packages
P, SN, ST, MS
P, SN, ST, MS
Features:
• Max. clock 10 MHz
• Low-power CMOS technology
- Max. Write Current: 5 mA at 5.5V, 10 MHz
- Read Current: 5 mA at 5.5V, 10 MHz
- Standby Current: 5 μA at 5.5V
• 4096 x 8-bit organization
• 32 byte page
• Self-timed erase and write cycles (5 ms max.)
• Block write protection
- Protect none, 1/4, 1/2 or all of array
• Built-in write protection
- Power-on/off data protection circuitry
- Write enable latch
- Write-protect pin
• Sequential read
• High reliability
- Endurance: >1M erase/write cycles
- Data retention: > 200 years
- ESD protection: > 4000V
• Temperature ranges supported;
- Industrial (I):
-40°C to +85°C
- Automotive (E):
-40°C to +125°C
• Standard and Pb-free packages available
Pin Function Table
Name
Function
CS Chip Select Input
SO Serial Data Output
WP Write-Protect
VSS Ground
SI
SCK
HOLD
Serial Data Input
Serial Clock Input
Hold Input
VCC Supply Voltage
Description:
The Microchip Technology Inc. 25AA320A/25LC320A
(25XX320A*) are 32k-bit Serial Electrically Erasable
PROMs. The memory is accessed via a simple Serial
Peripheral Interface (SPI) compatible serial bus. The
bus signals required are a clock input (SCK) plus sep-
arate data in (SI) and data out (SO) lines. Access to the
device is controlled through a Chip Select (CS) input.
Communication to the device can be paused via the
hold pin (HOLD). While the device is paused, transi-
tions on its inputs will be ignored, with the exception of
Chip Select, allowing the host to service higher priority
interrupts.
The 25XX320A is available in standard packages
including 8-lead PDIP and SOIC, and advanced
packaging including 8-lead MSOP, and 8-lead TSSOP.
All packages are Pb-free.
Package Types (not to scale)
TSSOP/MSOP
(ST, MS)
CS 1
SO 2
WP 3
VSS 4
8 VCC
7 HOLD
6 SCK
5 SI
PDIP/SOIC
(P, SN)
CS 1
SO 2
WP 3
VSS 4
8 VCC
7 HOLD
6 SCK
5 SI
*25XX320A is used in this document as a generic part number
for the 25AA320A, 25LC320A devices.
© 2007 Microchip Technology Inc.
DS21828C-page 1
1 page  
www.DataSheet4U.com
25AA320A/25LC320A
FIGURE 1-1: HOLD TIMING
CS
16
SCK
SO n + 2
n+1
17
18
n
17
16
19
High-Impedance
n
SI
n+2
n+1
n
Don’t Care
5
n
HOLD
n-1
n-1
FIGURE 1-2: SERIAL INPUT TIMING
CS
2
Mode 1,1
SCK Mode 0,0
5
6
SI MSB in
SO
7
High-Impedance
8
FIGURE 1-3: SERIAL OUTPUT TIMING
CS
SCK
SO
SI
9 10
13
MSB out
Don’t Care
14
4
12
11
3
LSB in
3
15
ISB out
Mode 1,1
Mode 0,0
© 2007 Microchip Technology Inc.
DS21828C-page 5
5 Page 
www.DataSheet4U.com
25AA320A/25LC320A
2.6 Write Status Register Instruction
(WRSR)
The Write Status Register instruction (WRSR) allows the
user to write to the nonvolatile bits in the STATUS
register as shown in Table 2-2. The user is able to
select one of four levels of protection for the array by
writing to the appropriate bits in the STATUS register.
The array is divided up into four segments. The user
has the ability to write-protect none, one, two or all four
of the segments of the array. The partitioning is
controlled as shown in Table 2-3.
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the STATUS register control the
programmable hardware write-protect feature. Hard-
ware write protection is enabled when WP pin is low
and the WPEN bit is high. Hardware write protection is
disabled when either the WP pin is high or the WPEN
bit is low. When the chip is hardware write-protected,
only writes to nonvolatile bits in the STATUS register
are disabled. See Table 2-4 for a matrix of functionality
on the WPEN bit.
See Figure 2-7 for the WRSR timing sequence.
TABLE 2-3: ARRAY PROTECTION
BP1
BP0
Array Addresses
Write-Protected
00
none
01
upper 1/4
(0C00h - 0FFFh)
10
upper 1/2
(0800h - 0FFFh)
11
all
(0000h - 0FFFh)
FIGURE 2-7: WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
CS
SCK
SI
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
Data to STATUS Register
0 00 00 0 01 7 6 54 3 2 10
High-Impedance
SO
Note: An internal write cycle (TWC) is initiated on the rising edge of CS after a valid write STATUS register
sequence.
© 2007 Microchip Technology Inc.
DS21828C-page 11
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet 25LC320A.PDF ] | |
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