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PDF IDT71V65902 Data sheet ( Hoja de datos )

Número de pieza IDT71V65902
Descripción (IDT71V65702 / IDT71V65902) Synchronous ZBT SRAMs
Fabricantes IDT 
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No Preview Available ! IDT71V65902 Hoja de datos, Descripción, Manual

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256K x 36, 512K x 18
3.3V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Flow-Through Outputs
IDT71V65702
IDT71V65902
Features
x 256K x 36, 512K x 18 memory configurations
x Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
x ZBTTM Feature - No dead cycles between write and read
cycles
x Internally synchronized output buffer enable eliminates the
need to control OE
x Single R/W (READ/WRITE) control pin
x 4-word burst capability (Interleaved or linear)
x Individual byte write (BW1-BW4) control (May tie active)
x Three chip enables for simple depth expansion
x 3.3V power supply (±5%)
x 2.5V (±5%) I/O Supply (VDDQ)
x Power down controlled by ZZ input
x Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA).
Description
The IDT71V65702/5902 are 3.3V high-speed 9,437,184-bit
(9 Megabit) synchronous SRAMs organized as 256K x 36 / 512K x
18. They are designed to eliminate dead bus cycles when turning the
bus around between reads and writes, or writes and reads. Thus they
have been given the name ZBTTM, or Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and on the next clock cycle the associated data cycle
occurs, be it read or write.
The IDT71V65702/5902 contain address, data-in and control signal
registers. The outputs are flow-through (no output data register). Output
enable is the only asynchronous signal and can be used to disable the
outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V65702/5902
to be suspended as long as necessary. All synchronous inputs are ignored
when CENishighandtheinternaldeviceregisterswillholdtheirprevious
values.
There are three chip enable pins (CE1, CE2, CE2) that allow the
user to deselect the device when desired. If any one of these three is not
asserted when ADV/LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state one cycle after the chip is deselected or a write
is initiated.
The IDT71V65702/5902 have an on-chip burst counter. In the burst
mode, the IDT71V65702/5902 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).
The IDT71V65702/5902 SRAMs utilize IDT’s latest high-performance
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm
100-pin plastic thin quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array (fBGA).
Pin Description Summary
A0-A18
Address Inputs
CE1, CE2, CE2
OE
R/W
Chip Enables
Output Enable
Read/Write Signal
CEN
BW1, BW2, BW3, BW4
Clock Enable
Individual Byte Write Selects
CLK Clock
ADV/LD
Advance Burst Address/Load New Address
LBO Linear/Interleaved Burst Order
ZZ Sleep Mode
I/O0-I/O31, I/OP1-I/OP4
Data Input/Output
VDD, VDDQ
Core Power, I/O Power
VSS Ground
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
Inp ut
I/ O
Sup p ly
Sup p ly
Synchro nous
Synchro nous
Asynchro nous
Synchro nous
Synchro nous
Synchro nous
N/A
Synchro nous
Static
Asynchro nous
Synchro nous
Static
Static
5315 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
©2004 Integrated Device Technology, Inc.
1
OCTOBER 2004
DSC-5315/08

1 page




IDT71V65902 pdf
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Range
Recommended Operating
Temperature and Supply Voltage
Grade
Ambient
Temperature(1)
VSS
VDD
VDDQ
Commercial
0°C to +70°C
0V 3.3V±5% 2.5V±5%
Industrial
-40°C to +85°C 0V 3.3V±5% 2.5V±5%
NOTES:
5315 tbl 05
1. During production testing, the case temperature equals the ambient temperature.
Pin Configuration — 256K x 36
I/OP3
I/O16
I/O17
VDDQ
VSS
I/O18
I/O19
I/O20
I/O21
VSS
VDDQ
I/O22
I/O23
VSS(1)
VDD
VDD(2)
VSS
I/O24
I/O25
VDDQ
VSS
I/O26
I/O27
I/O28
I/O29
VSS
VDDQ
I/O30
I/O31
I/OP4
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 80
2 79
3 78
4 77
5 76
6 75
7 74
8 73
9 72
10 71
11 70
12 69
13 68
14 67
15 66
16 65
17 64
18 63
19 62
20 61
21 60
22 59
23 58
24 57
25 56
26 55
27 54
28 53
29 52
30 51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
I/OP2
I/O15
I/O14
VDDQ
VSS
I/O13
I/O12
I/O11
I/O10
VSS
VDDQ
I/O9
I/O8
VSS
VSS(1)
VDD
ZZ
I/O7
I/O6
VDDQ
VSS
I/O5
I/O4
I/O3
I/O2
VSS
VDDQ
I/O1
I/O0
I/OP1
5315 drw 02
,
Top View
100 TQFP
NOTES:
1. Pins 14 and 66 do not have to be connected directly to VSS as long as the input voltage is VIL.
2. Pin 16 does not have to be connected directly to VDD as long as the input voltage is > VIH.
3. Pins 84 is reserved for a future 16M.
4. DNU = Do not use. Pins 38, 39, 42 and 43 are reserved for respective JTAG pins: TMS, TDI, TDO and TCK.
current die revision allows these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
The
6.452

5 Page





IDT71V65902 arduino
IDT71V65702, IDT71V65902, 256K x 36, 512K x 18, 3.3V Synchronous ZBT™ SRAMs with
3.3V or 2.5V I/O, Burst Counter, and Flow-Through Outputs
Commercial and Industrial Temperature Range
Device Operation - Showing Mixed Load, Burst, Deselect and NOOP Cycles(2)
Cycle
Address
R/W ADV/LD CE1(1) CEN BWx
OE
I/O Comments
n A0 H L L L X X D1 Load read
n+1 X
X H X L X L Q0 Burst read
n+2 A1 H L L L X L Q0+1 Load read
n+3 X X L H L X L Q1 Deselect or STOP
n+4 X X H X L X X Z NOOP
n+5 A2 H L L L X X Z Load read
n+6 X X H X L X L Q2 Burst read
n+7 X X L H L X L Q2+1 Deselect or STOP
n+8 A3 L L L L L X Z Load write
n+9 X X H X L L X D3 Burst write
n+10 A4
LL
L L L X D3+1 Load write
n+11 X
XL
H L X X D4 Deselect or STOP
n+12 X
X H X L X X Z NOOP
n+13 A5
LL
L L L X Z Load write
n+14 A6
HL
L L X X D5 Load read
n+15 A7
LL
L L L L Q6 Load write
n+16 X
X H X L L X D7 Burst write
n+17 A8
HL
L L X X D7+1 Load read
n+18 X
X H X L X L Q8 Burst read
n+19 A9
LL
L L L L Q8+1 Load write
NOTES:
1. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
2. H = High; L = Low; X = Don't Care; Z = High Impedence.
5315 tbl 12
6.1412

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