DataSheet.es    


PDF GS816236BB Data sheet ( Hoja de datos )

Número de pieza GS816236BB
Descripción (GS816218 / GS816236BB) S/DCD Sync Burst SRAMs
Fabricantes GSI Technology 
Logotipo GSI Technology Logotipo



Hay una vista previa y un enlace de descarga de GS816236BB (archivo pdf) en la parte inferior de esta página.


Total 30 Páginas

No Preview Available ! GS816236BB Hoja de datos, Descripción, Manual

www.DataSheet4U.com
Preliminary
GS816218/36BB
119--Bump BGA
Commercial Temp
Industrial Temp
1M x 18, 512K x 36
18Mb S/DCD Sync Burst SRAMs
250 MHz150 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 2.5 V or 3.3 V +10%/–10% core power supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119-bump BGA package
Functional Description
Applications
The GS816218/36BB is an 18,874,368-bit high performance
synchronous SRAM with a 2-bit burst address counter. Although of a
type originally developed for Level 2 Cache applications supporting
high performance CPUs, the device now finds application in
synchronous SRAM applications, ranging from DSP main store to
networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control inputs
(ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are
synchronous and are controlled by a positive-edge-triggered clock
input (CK). Output enable (G) and power down control (ZZ) are
asynchronous inputs. Burst cycles can be initiated with either ADSP
or ADSC inputs. In Burst mode, subsequent burst addresses are
generated internally and are controlled by ADV. The burst address
counter may be configured to count in either linear or interleave order
with the Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the user
via the FT mode . Holding the FT mode pin low places the RAM in
Flow Through mode, causing output data to bypass the Data Output
Register. Holding FT high places the RAM in Pipeline mode,
activating the rising-edge-triggered Data Output Register.
SCD and DCD Pipelined Reads
The GS816218/36BB is an SCD (Single Cycle Deselect) and DCD
(Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs
pipeline disable commands to the same degree as read commands.
SCD SRAMs pipeline deselect commands one stage less than read
commands. SCD RAMs begin turning off their outputs immediately
after the deselect command has been captured in the input registers.
DCD RAMs hold the deselect command for one full cycle and then
begin turning off their outputs just after the second rising edge of
clock. The user may configure this SRAM for either mode of
operation using the SCD mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW)
input combined with one or more individual byte write signals (Bx).
In addition, Global Write (GW) is available for writing all bytes at one
time, regardless of the Byte Write control inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low) for
multi-drop bus applications and normal drive strength (ZQ floating or
high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of
the ZZ signal, or by stopping the clock (CK). Memory data is retained
during Sleep mode.
Core and Interface Voltages
The GS816218/36BB operates on a 2.5 V or 3.3 V power supply. All
input are 3.3 V and 2.5 V compatible. Separate output power (VDDQ)
pins are used to decouple output noise from the internal circuits and
are 3.3 V and 2.5 V compatible.
Pipeline
3-1-1-1
Flow Through
2-1-1-1
Parameter Synopsis
-250 -200 -150 Unit
tKQ
tCycle
Curr (x18)
Curr (x36)
tKQ
tCycle
Curr (x18)
Curr (x36)
2.5 3.0 3.8 ns
4.0 5.0 6.7 ns
280 230 185 mA
330 270 210 mA
5.5 6.5 7.5 ns
5.5 6.5 7.5 ns
210 185 170 mA
240 205 190 mA
Rev: 1.0 9/2004
1/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology

1 page




GS816236BB pdf
GS816218/36B Block Diagram
Preliminary
GS816218/36BB
A0–An
LBO
ADV
CK
ADSC
ADSP
GW
BW
BA
BB
BC
BD
Register
DQ
A0
A1
D0 Q0
D1 Q1
Counter
Load
A0
A1
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
DQ
Register
E1 D Q
Register
DQ
FT
G
ZZ Power Down
Control
Note: Only x36 version shown for simplicity.
SCD
A
Memory
Array
Q
36
D
36
4
36
36
36
36
DQx1–DQx9
Rev: 1.0 9/2004
5/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology

5 Page





GS816236BB arduino
Preliminary
GS816218/36BB
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
Description
Value
Unit
VDD Voltage on VDD Pins
0.5 to 4.6
V
VDDQ
Voltage in VDDQ Pins
0.5 to 4.6
V
VI/O
Voltage on I/O Pins
0.5 to VDDQ +0.5 (4.6 V max.)
V
VIN
Voltage on Other Input Pins
0.5 to VDD +0.5 (4.6 V max.)
V
IIN Input Current on Any Pin
+/20
mA
IOUT Output Current on Any I/O Pin
+/20
mA
PD Package Power Dissipation
1.5 W
TSTG Storage Temperature
55 to 125
oC
TBIAS
Temperature Under Bias
55 to 125
oC
Note:
Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended
Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of
this component.
Power Supply Voltage Ranges
Parameter
Symbol Min. Typ. Max. Unit Notes
3.3 V Supply Voltage
VDD3
3.0
3.3
3.6
V
2.5 V Supply Voltage
VDD2
2.3
2.5
2.7
V
3.3 V VDDQ I/O Supply Voltage
VDDQ3
3.0
3.3
3.6
V
2.5 V VDDQ I/O Supply Voltage
VDDQ2
2.3
2.5
2.7
V
Notes:
1. The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-
tions quoted are evaluated for worst case in the temperature range marked on the device.
2. Input Under/overshoot voltage must be 2 V > Vi < VDDn+2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.
Rev: 1.0 9/2004
11/31
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2004, GSI Technology

11 Page







PáginasTotal 30 Páginas
PDF Descargar[ Datasheet GS816236BB.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
GS816236B(GS816218x - GS816272c) Sync Burst SRAMsGSI Technology
GSI Technology
GS816236BB(GS816218 / GS816236BB) S/DCD Sync Burst SRAMsGSI Technology
GSI Technology

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar