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PDF GS816218B Data sheet ( Hoja de datos )

Número de pieza GS816218B
Descripción (GS816218x - GS816272c) Sync Burst SRAMs
Fabricantes GSI Technology 
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GS816218(B/D)/GS816236(B/D)/GS816272(C)
119-, 165-, & 209-Bump BGA
Commercial Temp
Industrial Temp
1M x 18, 512K x 36, 256K x 72
18Mb Sync Burst SRAMs
250 MHz–133 MHz
2.5 V or 3.3 V VDD
2.5 V or 3.3 V I/O
Features
• FT pin for user-configurable flow through or pipeline operation
• Single/Dual Cycle Deselect selectable
• IEEE 1149.1 JTAG-compatible Boundary Scan
• ZQ mode pin for user-selectable high/low output drive
• 2.5 V or 3.3 V +10%/–10% core power supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Default to SCD x18/x36 Interleaved Pipeline mode
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 119-, 165-, and 209-bump BGA package
Functional Description
Applications
The GS816218(B/D)/GS816236(B/D)/GS816272(C) is an
18,874,368-bit high performance synchronous SRAM with a 2-bit
burst address counter. Although of a type originally developed for
Level 2 Cache applications supporting high performance CPUs,
the device now finds application in synchronous SRAM
applications, ranging from DSP main store to networking chip set
support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW,
GW) are synchronous and are controlled by a positive-edge-
triggered clock input (CK). Output enable (G) and power down
control (ZZ) are asynchronous inputs. Burst cycles can be initiated
with either ADSP or ADSC inputs. In Burst mode, subsequent
burst addresses are generated internally and are controlled by
ADV. The burst address counter may be configured to count in
either linear or interleave order with the Linear Burst Order (LBO)
input. The Burst function need not be used. New addresses can be
loaded on every cycle with no degradation of chip performance.
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by the
user via the FT mode . Holding the FT mode pin low places the
RAM in Flow Through mode, causing output data to bypass the
Data Output Register. Holding FT high places the RAM in
Pipeline mode, activating the rising-edge-triggered Data Output
Register.
SCD and DCD Pipelined Reads
The GS816218(B/D)/GS816236(B/D)/GS816272(C) is a SCD
(Single Cycle Deselect) and DCD (Dual Cycle Deselect)
pipelined synchronous SRAM. DCD SRAMs pipeline disable
commands to the same degree as read commands. SCD SRAMs
pipeline deselect commands one stage less than read commands.
SCD RAMs begin turning off their outputs immediately after the
deselect command has been captured in the input registers. DCD
RAMs hold the deselect command for one full cycle and then
begin turning off their outputs just after the second rising edge of
clock. The user may configure this SRAM for either mode of
operation using the SCD mode input.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write control
inputs.
FLXDrive™
The ZQ pin allows selection between high drive strength (ZQ low)
for multi-drop bus applications and normal drive strength (ZQ
floating or high) point-to-point applications. See the Output Driver
Characteristics chart for details.
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High)
of the ZZ signal, or by stopping the clock (CK). Memory data is
retained during Sleep mode.
Core and Interface Voltages
The GS816218(B/D)/GS816236(B/D)/GS816272(C) operates on
a 2.5 V or 3.3 V power supply. All input are 3.3 V and 2.5 V
compatible. Separate output power (VDDQ) pins are used to
decouple output noise from the internal circuits and are 3.3 V and
2.5 V compatible.
Parameter Synopsis
Pipeline
3-1-1-1
3.3 V
Flow Through
2-1-1-1
3.3 V
tKQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
tKQ
tCycle
Curr (x18)
Curr (x36)
Curr (x72)
-250
2.5
4.0
280
330
n/a
5.5
5.5
175
200
n/a
-225
2.7
4.4
255
300
n/a
6.0
6.0
165
190
n/a
-200
3.0
5.0
230
270
350
6.5
6.5
160
180
225
-166
3.4
6.0
200
230
300
7.0
7.0
150
170
115
-150
3.8
6.7
185
215
270
7.5
7.5
145
165
210
-133
4.0
7.5
165
190
245
8.5
8.5
135
150
185
Unit
ns
ns
mA
mA
mA
ns
ns
mA
mA
mA
Rev: 2.17 11/2004
1/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology

1 page




GS816218B pdf
GS816218(B/D)/GS816236(B/D)/GS816272(C)
165-Bump BGA—x36 Common I/O—Top View (Package D)
1 2 3 4 5 6 7 8 9 10 11
A NC A E1 BC BB E3 BW ADSC ADV A NC A
B NC A E2 BD BA CK GW G ADSP A NC B
C DQC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQB C
D DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB D
E DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB E
F DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB F
G DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB G
H FT MCL NC VDD VSS VSS VSS VDD NC ZQ ZZ H
J DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA J
K DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA K
L DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA L
M DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA M
N
DQD SCD VDDQ VSS
NC
A
NC VSS VDDQ NC DQA
N
P
NC NC
A
A TDI A1 TDO A
A
A
A
P
R LBO NC A A TMS A0 TCK A A A A
R
11 x 15 Bump BGA—13mm x 15 mm Body—1.0 mm Bump Pitch
Rev: 2.17 11/2004
5/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology

5 Page





GS816218B arduino
GS816218(B/D)/GS816236(B/D)/GS816272(C)
Mode Pin Functions
Mode Name
Pin Name State
Function
Burst Order Control
LBO
L
H
Linear Burst
Interleaved Burst
Output Register Control
L
FT
H or NC
Flow Through
Pipeline
Power Down Control
L or NC
ZZ H
Active
Standby, IDD = ISB
Single/Dual Cycle Deselect Control
SCD
L
H or NC
Dual Cycle Deselect
Single Cycle Deselect
FLXDrive Output Impedance Control
ZQ
L
H or NC
High Drive (Low Impedance)
Low Drive (High Impedance)
9th Bit Enable
PE
L
H or NC
Activate DQPx I/Os (x18/x36 mode)
Deactivate DQPx I/Os (x16/x32 mode)
Note:
There are pull-up devices on the ZQ, SCD, and FT pins and a pull-down device on the ZZ pin, so those input pins can be unconnected and the
chip will operate in the default states as specified in the above tables.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 10 11 00
3rd address 10 11 00 01
4th address 11 00 01 10
Note:
The burst counter wraps to initial state on the 5th clock.
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0]
1st address 00 01 10 11
2nd address 01 00 11 10
3rd address 10 11 00 01
4th address 11 10 01 00
Note:
The burst counter wraps to initial state on the 5th clock.
BPR 1999.05.18
Rev: 2.17 11/2004
11/41
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 1999, GSI Technology

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