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PDF KSZ8721BT Data sheet ( Hoja de datos )
| Número de pieza | KSZ8721BT | |
| Descripción | 2.5V 10/100BasTX/FX MII Physical Layer Transceiver | |
| Fabricantes | Micrel Semiconductor | |
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KS8721B/BT
www.DataSheet4U.com
Micrel
KS8721B/BT
2.5V 10/100BasTX/FX MII Physical Layer Transceiver
Rev. 2.2
General Description
Operating at 2.5 volts to meet low voltage and low power
requirements, the KS8721B/BT is a 10BaseT/100BaseTX/
FX Physical Layer Transceiver, which provides an MII to
transmit and receive data. It contains the 10BaseT Physical
Medium Attachment (PMA), Physical Medium Dependent
(PMD), and Physical Coding Sub-layer (PCS) functions.
Moreover, the KS8721B/BT has on-chip 10BaseT output
filtering, which eliminates the need for external filters and
allows a single set of line magnetics to be used to meet
requirements for both 100BaseTX and 10BaseT.
The KS8721B/BT can automatically configure itself for 100 or
10 Mbps and full or half duplex operation, using on-chip Auto-
Negotiation algorithm. It is an ideal choice of physical layer
transceiver for 100BaseTX/10BaseT applications.
Data sheets and support documentation can be found on
Micrel’s web site at www.micrel.com.
Features
• Single chip 100BaseTX/100BaseFX/10BaseT physical
layer solution
• 2.5V CMOS design, power consumption <200mW
(excluding output driver current )
• Fully compliant to IEEE 802.3u standard
• Supports Media Independent Interface (MII) and
Reduced MII (RMII)
• Supports 10BaseT, 100BaseTX and 100BaseFX with
Far_End_Fault Detection
• Supports power down mode and power saving mode
• Configurable through MII serial management ports or via
external control pins
• Supports auto-negotiation and manual selection for
10/100Mbps speed and full/half-duplex mode
• On-chip built-in analog front end filtering for both
100BaseTX and 10BaseT
Functional Diagram
TX+
Transmitter
TX-
10/100
Pulse
Shaper
RX+
RX-
Adaptive EQ
Base Line
Wander Correction
MLT3 Decoder
NRZI/NRZ
10BaseT
Receiver
XI
PLL
XO
NRZ/NRZI
MLT3 Encoder
Clock
Recovery
Auto
Negotiation
Power
Down or
Saving
PWRDWN
4B/5B Encoder
Scrambler
Parallel/Serial
Parallel/Serial
Manchester Encoder
4B/5B Decoder
Descrambler
Serial/Parallel
Manchester Decoder
Serial/Parallel
MII/RMII
Registers
and
Controller
Interface
LED
Driver
TXD3
TXD2
TXD1
TXD0
TXER
TXC
TXEN
CRS
COL
MDIO
MDC
RXD3
RXD2
RXD1
RXD0
RXER
RXDV
RXC
LINK
COL
FDX
SPD
Micrel, Inc. • 1849 Fortune Drive • San Jose, CA 95131 • USA • tel + 1 (408) 944-0800 • fax + 1 (408) 944-0970 • http://www.micrel.com
August 2003 1 KS8721B/BT
1 page  
KS8721B/BT
Micrel
Absolute Maximum Ratings ..................................................................................................................................... 22
Operating Ratings ..................................................................................................................................................... 22
Electrical Characteristics .......................................................................................................................................... 22
Timing Diagrams ....................................................................................................................................................... 24
Selection of Isolation Transformers ........................................................................................................................ 30
Selection of Reference Crystals ............................................................................................................................... 30
Package Outline and Dimensions ............................................................................................................................ 31
August 2003 5 KS8721B/BT
5 Page 
KS8721B/BT
Micrel
Introduction
100BaseTX Transmit
The 100BaseTX transmit function performs parallel to serial conversion, NRZ to NRZI conversion, MLT-3 encoding and
transmission. The circuitry starts with a parallel to serial conversion, which converts the 25MHz, 4-bit nibbles into a 125 MHz
serial bit stream. The incoming data is clocked in at the positive edge of the TXC signal. The serialized data is further converted
from NRZ to NRZI format, and then transmitted in MLT3 current output. The output current is set by an external 1% 6.49kΩ
resistor for the 1: 1 transformer ratio. It has a typical rise/fall times of 4 ns and complies to the ANSI TP-PMD standard regarding
amplitude balance, overshoot and timing jitters. The wave-shaped 10BaseT output driver is also incorporated into the
100BaseTX driver.
100BaseTX Receive
The 100BaseTX receive function performs adaptive equalization, DC restoration, MLT-3 to NRZI conversion, data and clock
recovery, NRZI to NRZ conversion, and serial to parallel conversion. The receiving side starts with the equalization filter to
compensate inter-symbol interference (ISI) over the twisted pair cable. Since the amplitude loss and phase distortion are a
function of the length of the cable, the equalizer has to adjust its characteristic to optimize the performance. In this design, the
variable equalizer will make an initial estimation based on comparisons of incoming signal strength against some known cable
characteristics, then tunes itself for optimization. This is an ongoing process and can self adjust against the environmental
changes such as temperature variations.
The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used to
compensate effect of base line wander and improve the dynamic range. The differential data conversion circuit converts the
MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125MHz clock from the edges of the NRZI signal. This recovered clock is then used to
convert the NRZI signal into the NRZ format. Finally, the NRZ serial data is converted to 4-bit parallel 4B nibbles. A synchronized
25MHz RXC is generated so that the 4B nibbles is clocked out at the negative edge of RCK25 and is valid for the receiver at
the positive edge. When no valid data is present, the clock recovery circuit is locked to the 25MHz reference clock and both
TXC and RXC clocks continue to run.
PLL Clock Synthesizer
The KS8721B/BT generates 125MHz, 25MHz and 20MHz clocks for system timing. An internal crystal oscillator circuit provides
the reference clock for the synthesizer.
Scrambler/De-scrambler (100BaseTX only)
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce EMI and baseline wander.
10BaseT Transmit
When TXEN (transmit enable) goes high, data encoding and transmission will begin. The KS8721B/BT will continue to encode
and transmit data as long as TXEN remains high. The data transmission will end when TXEN goes low. The last transition
occurs at the boundary of the bit cell if the last bit is zero, or at the center of the bit cell if the last bit is one. The output driver
is incorporated into the 100Base driver to allow transmission with the same magnetics. They are internally wave-shaped and
pre-emphasized into outputs with a typical 2.5V amplitude. The harmonic contents are at least 27dB below the fundamental
when driven by an all-ones Manchester-encoded signal.
10BaseT Receive
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a
PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A
squelch circuit rejects signals with levels less than 300mV or with short pulse widths in order to prevent noises at the RX+ or
RX- input from falsely trigger the decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal
and the KS8721B/BT decodes a data frame. This activates the carrier sense (CRS) ad RXDV signals and makes the receive
data (RXD) available. The receive clock is maintained active during idle periods in between data reception.
SQE and Jabber Function (10BaseT only)
In 10BaseT operation, a short pulse will be put out on the COL pin after each packet is transmitted. This is required as a test
of the 10BaseT transmit/receive path and is called SQE test. The 10BaseT transmitter will be disabled and COL will go high
if TXEN is High for more than 20ms (Jabbering). If TXEN then goes low for more than 250ms, the 10BaseT transmitter will be
re-enabled and COL will go Low.
Auto-Negotiation
The KS8721B/BT performs auto-negotiation by hardware strapping option (pin 29) or software (Register 0.12). It will
automatically choose its mode of operation by advertising its abilities and comparing them with those received from its link
partner whenever auto-negotiation is enabled. It can also be configured to advertise 100BaseTX or 10BaseT in either full- or
half-duplex mode (please refer to “Auto-Negotiation” ). The auto-negotiation is disabled in the FX mode.
August 2003 11 KS8721B/BT
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KSZ8721BT.PDF ] | |
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