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PDF 80220 Data sheet ( Hoja de datos )

Número de pieza 80220
Descripción (80220 / 80221) 100BASE-TX/10BASE-T Ethernet Media Interface Adapter
Fabricantes LSI 
Logotipo LSI Logotipo



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80228002/8200/82022211
100BASE-TX/10BASE-T Ethernet
Media Interface Adapter
98184
Features
s Single Chip 100Base-TX / 10Base-T Physical Layer
Solution
s Dual Speed - 100/10 Mbps
s Half And Full Duplex
s MII Interface To Ethernet Controller
s MI Interface For Configuration & Status
s Optional Repeater Interface
s AutoNegotiation: 10/100, Full/Half Duplex
s Meets All Applicable IEEE 802.3, 10Base-T,
100Base-TX Standards
s On Chip Wave Shaping - No External Filters
Required
s Adaptive Equalizer
s Baseline Wander Correction
s Interface to External 100Base-T4 PHY
s LED Outputs
- Link
- Activity
- Collision
- Full Duplex
- 10/100
- User Programmable
s Many User Features And Options
s Few External Components
s Pin configuration
- 44L PLCC - 80220
- 64L LQFP - 80221
Note: Check for latest Data Sheet revision
before starting any designs.
SEEQ Data Sheets are now on the Web, at
www.lsilogic.com.
This document is an LSI Logic document. Any
reference to SEEQ Technology should be
considered LSI Logic.
Description
The 80220/80221 are highly integrated analog interface
IC's for twisted pair Ethernet applications. The 80220/
80221 can be configured for either 100 Mbps (100Base-
TX) or 10 Mbps (10Base-T) Ethernet operation. The
80220 is packaged in a 44L package, while the 80221 is
packaged in a 64L package and contains a few more
features.
The 80220/80221 consist of 4B5B/Manchester encoder/
decoder, scrambler/descrambler, 100Base-TX/10Base-T
twisted pair transmitter with wave shaping and output
driver, 100Base-TX/10Base-T twisted pair receiver with
on chip equalizer and baseline wander correction, clock
and data recovery, AutoNegotiation, controller interface
(MII), and serial port (MI).
The addition of internal output waveshaping circuitry and
on-chip filters eliminates the need for external filters nor-
mally required in 100Base-TX and 10Base-T applications.
The 80220/80221 can automatically configure itself for
100 or 10 Mbps and Full or Half Duplex operation with the
on-chip AutoNegotiation algorithm.
The 80220/80221 can access eleven 16-bit registers though
the Management Interface (MI) serial port. These registers
contain configuration inputs, status outputs, and device
capabilities.
The 80220/80221 are ideal as media interfaces for
100Base-TX/10Base-T adapter cards, motherboards, re-
peaters, switching hubs, and external PHY's.
MD400159/E
4-11

1 page




80220 pdf
80220/80221
1.0 Pin Description
Pin# Pin
44L 64L Name
28 32 VCC6
24 25 VCC5
11 8 VCC4
10 7 VCC3
1 57 VCC2
44 56 VCC1
I/O Description
Positive Supply. 5 ± 5% Volts
27 31 GND6
23 23 GND5
36 41 GND4
9 6 GND3
4 60 GND2
41 52 GND1
Ground. 0 Volts
42 54 TPO+ O Twisted Pair Transmit Output, Positive.
43 55 TPO -
2 58 TPI+
O Twisted Pair Transmit Output, Negative.
I Twisted Pair Receive Input, Positive.
3 59 TPI -
I Twisted Pair Receive Input, Negative.
40 50 REXT
Transmit Current Set. An external resistor connected between this pin and GND will set the
output current level for the twisted pair outputs.
37 42 OSCIN I Clock Oscillator Input. There must be either a 25 Mhz crystal between this pin and GND or
a 25 Mhz clock applied to this pin. TX_CLK output is generated from this input.
29 34 TX_CLK O
Transmit Clock Output. This controller interface output provides a clock to an external
controller. Transmit data from the controller on TXD, TX_EN, and TX_ER is clocked in on
rising edges of TX_CLK and OSCIN.
35 40 TX_EN I Transmit Enable Input. This controller interface input has to be asserted active high to
indicate that data on TXD and TX_ER is valid, and it is clocked in on rising edges of TX_CLK
and OSCIN.
33 38 TXD3
32 37 TXD2
31 36 TXD1
30 35 TXD0
I Transmit Data Input. These controller interface inputs contain input nibble data to be
transmitted on the TP outputs, and they are clocked in on rising edges of TX_CLK and OSCIN
when TX_EN is asserted.
34 39 TX_ER / I
TXD4
Transmit Error Input. This controller interface input causes a special pattern to be
transmitted on the twisted pair outputs in place of normal data, and it is clocked in on rising
edges of TX_CLK when TX_EN is asserted.
25 26 RX_CLK O
If the device is placed in the Bypass 4B5B Encoder mode, this pin is reconfigured to be the
fifth TXD transmit data input, TXD4.
Receive Clock Output. This controller interface output provides a clock to an external
controller. Receive data on RXD, RX_DV, and RX_ER is clocked out on falling edges of
RX_CLK.
16 13 CRS
O Carrier Sense Output. This controller interface output is asserted active high when valid data
is detected on the receive twisted pair inputs, and it is clocked out on falling edges of RX_CLK.
17 14 RX_DV O Receive Data Valid Output. This controller interface output is asserted active high when valid
decoded data is present on the RXD outputs, and it is clocked out on falling edges of RX_CLK.
19 19 RXD3
20 20 RXD2
21 21 RXD1
22 22 RXD0
O Receive Data Output. These controller interface outputs contain receive nibble data from
the TP input, and they are clocked out on falling edges of RX_CLK.
MD400159/E
4-55

5 Page





80220 arduino
80220/80221
TX_EN = 0
IDLE
PREAMBLE
PRMBLE
62 BT
START
OF
FRAME
DELIM.
SFD
TX_EN = 1
DATA 1
DATA NIBBLES
DATA 2
DATA N-1
DATA N
2 BT
TX_EN = 0
IDLE
PREAMBLE = [ 1 0 1 0 ... ] 62 BITS LONG
SFD = [ 1 1 ]
DATAn = [ BETWEEN 64-1518 DATA BYTES ]
IDLE = TX_EN = 0
a.) MII Frame Format
MII
NIBBLE
STREAM
FIRST BIT
MAC’s SERIAL BIT STREAM
LSB D0 D1 D2 D3 D4 D5 D6 D7 MSB
FIRST
NIBBLE
SECOND
NIBBLE
TXD0 / RXD0
TXD1 / RXD1
TXD2 / RXD2
TXD3 / RXD3
b.) MII Nibble Order
Signals
TXDO
TXD1
TXD2
TXD3
TX_EN
Bit Value
X X 11 1 1 1 1 1 1 1 1 1 1
XX0 0 0 0 0 0 0 0 0 0 0
XX1 1 1 1 1 1 1 1 1 1 1
XX0 0 0 0 0 0 0 0 0 0 0
0011111111111
11
00
11
00
11
1 12 1
000
111
001
111
1. 1st preamble nibble transmitted.
2. 1st sfd nibble transmittted.
3. 1st data nibble transmitted.
4. D0 thru D7 are the first 8 bits of the data field.
c.) Transmit Preamble and SFD bits
D03 D44
D1 D5
D2 D6
D3 D7
11
Signals Bit Value
RXDO X 11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 12 1
RXD1 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RXD2 X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
RXD3 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
RX_DV 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1. 1st preamble nibble received. Depending on mode, device may eliminate
either all or some of the preamble nibbles, up to 1st SFD nibble.
2. 1st sfd nibble received.
3. 1st data nibble received.
4. D0 thru D7 are the first 8 bits of the data field.
d.) Receive Preamble and SFD Bits
Figure 3. MII Frame Format
D03 D44
D1 D5
D2 D6
D3 D7
11
MD400159/E
41-111

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