PDF IDTCV123 Data sheet ( Hoja de datos )

Número de pieza	IDTCV123
Descripción	PROGRAMMABLE FLEXPC CLOCK
Fabricantes	IDT
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No Preview Available ! www.DataSheet4U.com IDTCV123 PROGRAMMABLEFLEXPC™ CLOCKFORP4PROCESSOR COMMERCIALTEMPERATURERANGE PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR IDTCV123 FEATURES: • One high precision PLL for CPU, with SSC and N program- mable • One high precision PLL for SRC/PCI/SATA, SSC and N pro- grammable • One high precision PLL for 96MHz/48MHz • Band-gap circuit for differential outputs • Supports spread spectrum modulation, down spread 0.5% • Supports SMBus block read/write, index read/write • Selectable output strength for REF • Allows for CPU frequency to change to a higher frequency for maximum system computing power • Available in SSOP package OUTPUTS: • 20.7V current –mode differential CPU CLK pair • 80.7V current –mode differential SRC CLK pair, one dedicated for SATA • One CPU_ITP/SRC selectable CLK pair • 8PCI, 3 free running, 33.3MHz • 196MHz,148MHz • 2REF DESCRIPTION: IDTCV123 is a 56 pin clock device. The CPU output buffer is designed to support up to 400MHz processor. This chip has three PLLs inside for CPU/ SRC/PCI, SATA, and 48MHz/DOT96 IO clocks. One dedicated PLL for Serial ATA clock provides high accuracy frequency. This device also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance. Static PLL frequency divide error can be as low as 36 ppm, worse case 114 ppm, providing high accuracy output clock. Each CPU/SRC/PCI, SATA clock has its own Spread Spectrum selection, which allows for isolated changes instead of affecting other clock groups. KEY SPECIFICATION: • CPU/SRC CLK cycle to cycle jitter < 85ps • SATA CLK cycle to cycle jitter < 85ps • PCI CLK cycle to cycle jitter < 250ps • Static PLL frequency divide error < 114 ppm • Static PLL frequency divide error for 48MHz < 5 ppm FUNCTIONAL BLOCK DIAGRAM X1 X2 SDATA SCLK XTAL Osc Amp SM Bus Controller VTT_PWRGD#/PD FSA.B.C Control Logic PLL1 SSC N Programmable CPU CLK Output Buffers Stop Logic IREF ITP_EN PLL2 SSC N Programmable SRC CLK Output Buffer Stop Logic IREF PLL3 48MHz/96MHz Output BUffer The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE © 2004 Integrated Device Technology, Inc. 1 CPU[1:0] CPU_ITP/SRC6 REF[0:1] SRC[6:0] SATA_SRC PCI[5:0], PCIF[2:0] 48MHz DOT96 MAY 2004 DSC-6538/4 1 page IDTCV123 PROGRAMMABLEFLEXPC™ CLOCKFORP4PROCESSOR COMMERCIALTEMPERATURERANGE CONTROL REGISTERS N PROGRAMMING PROCEDURE • Use Index byte write. • For N programming, the user only needs to access Byte17, Byte 25, and Byte8. 1. Write Byte17 for CPU PLL N, CPU f = N* Resolution, see resolution table below Byte17. 2. Write Byte25 for SRC PLL N, SRC f = N*0.666667, PCI = SRC f /3, SATA f = SRC f. 3. Enable N Programming bit, Byte8 bit1. Once this bit is enabled, any N value will be changed on the fly. • Center spread only works when the N Programming bit is enabled. Down spread is OK even N Programming bit is disabled • It is OK to change N value to any value on the bench test board. In the system, IDT recommends the stepping change. It is unknown how much the system can sustain for each stepping change; the estimate is about 5. If the N changes too much in one step, the system will likely hang. • Note that SATA is with SRC PLL. This SATA Hard Drive might not operate during SRC N programming. Most of the Bytes, from Byte8-Byte31, are used to adjust output waveforms and SSC modulation profiles. The power on setting will be changed according to each power on frequency selection. To avoid mistakes, don’t write on those byte (be careful about Block Write). It is suggested to use the Index Byte write to access bytes. SSC MAGNITUDE CONTROL, SMC SMC[2:0] 000 -0.25 001 -0.5 010 -0.75 011 -1 100 ±0.125 101 ±0.25 110 ±0.375 111 ±0.5 FREQUENCY SELECTION TABLE FS_C, B, A CPU 101 100 001 133 011 166 010 200 000 266 100 333 110 400 111 RESERVE RESOLUTION CPU (MHz) 100 133 166 200 266 333 400 Resolution 0.666667 0.666667 1.333333 1.333333 1.333333 2.666667 2.666667 N= 150 200 125 150 200 125 150 5 5 Page IDTCV123 PROGRAMMABLEFLEXPC™ CLOCKFORP4PROCESSOR COMMERCIALTEMPERATURERANGE ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE DIFFERENTIAL PAIR(1) Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF Symbol ZO VOH3 VOL3 VHIGH VLOW VOVS VUDS VCROSS(ABS) d - VCROSS ppm TPERIOD Parameter Test Conditions Current Source Output Impedance(2) VO = VX Output HIGH Voltage IOH = -1mA Output LOW Voltage IOL = 1mA Voltage HIGH(2) Voltage LOW(2) Max Voltage(2) Statistical measurement on single-ended signal using oscilloscope math function Measurement on single-ended signal using absolute value Min Voltage(2) Crossing Voltage (abs)(2) Crossing Voltage (var)(2) Variation of crossing over all edges Long Accuracy(2,3) See TPERIOD Min. - Max. values 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread Average Period(3) 200MHz nominal/spread Min. 3000 2.4 — 660 –150 — –300 250 — –300 2.4993 2.9991 3.7489 4.9985 Typ. — — — — — — — — — — — — — — Max. — — 0.4 850 150 1150 — 550 140 300 2.5008 3.0009 3.7511 5.0015 Unit Ω V V mV mV mV mV ppm ns 166.66MHz nominal/spread 133.33MHz nominal/spread 100MHz nominal/spread 5.9982 7.4978 9.997 — — — 6.0018 7.5023 10.003 TABSMIN Absolute Min Period(2,3) 96MHz nominal 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread 200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100MHz nominal/spread 10.4135 2.4143 2.9141 3.6639 4.9135 5.9132 7.4128 9.912 — — — — — — — — 10.4198 — — — — — — — ns tR tF d-tR d-tF dT3 tSK3 tJCYC-CYC Rise Time(2) Fall Time(2) Rise Time Variation(2) Fall Time Variation(2) Duty Cycle(2) Skew(2) Jitter, Cycle to Cycle(2) 96MHz nominal VOL = 0.175V, VOH = 0.525V VOL = 0.175V, VOH = 0.525V Measurement from differential waveform VT = 50% Measurement from differential waveform 10.1635 — — 175 — 700 ps 175 — 700 ps — — 125 ps — — 125 ps 45 — 55 % — — 100 ps — — 85 ps NOTES: 1. SRC clock outputs run only at 100MHz or 200MHz. Specs for 133.33 and 166.66 do not apply to SRC clock pair. 2. This parameter is guaranteed by design, but not 100% production tested. 3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz. 11 11 Page

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