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PDF LFEC15 Data sheet ( Hoja de datos )

Número de pieza LFEC15
Descripción (LFEC Series) LatticeECP/EC Family Data Sheet
Fabricantes Lattice Semiconductor 
Logotipo Lattice Semiconductor Logotipo



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No Preview Available ! LFEC15 Hoja de datos, Descripción, Manual

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LatticeECP/EC Family Data Sheet
Version 01.3

1 page




LFEC15 pdf
Lattice Semiconductor
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-1. Simplified Block Diagram, LatticeECP/EC Device (Top Level)
Programmable I/O Cell
(PIC) includes sysIO
Interface
sysMEM Embedded
Block RAM (EBR)
sysCONFIG Programming
Port (includes dedicated
and dual use pins)
JTAG Port
PFF (PFU without
RAM)
sysCLOCK PLL
Programmable
Functional Unit (PFU)
Figure 2-2. Simplified Block Diagram, LatticeECP-DSP Device (Top Level)
Programmable I/O Cell
(PIC) includes sysIO
Interface
sysMEM Embedded
Block RAM (EBR)
sysCONFIG Programming
Port (includes dedicated
and dual use pins)
sysDSP Block
Programmable
Functional Unit (PFU)
2-2
JTAG Port
PFF (Fast PFU
without RAM/ROM)
sysCLOCK PLL

5 Page





LFEC15 arduino
Lattice Semiconductor
Architecture
LatticeECP/EC Family Data Sheet
Secondary Clock Sources
LatticeECP/EC devices have four secondary clock resources per quadrant. The secondary clock branches are
tapped at every PFU. These secondary clock networks can also be used for controls and high fanout data. These
secondary clocks are derived from four clock input pads and 16 routing signals as shown in Figure 2-7.
Figure 2-7. Secondary Clock Sources
From
Routing
From
Routing
From
Routing
From
Routing
From Routing
From Routing
From Routing
From Routing
20 Secondary Clock Sources
To Quadrant Clock Selection
From Routing
From Routing
From Routing
From Routing
From
Routing
From
Routing
From
Routing
From
Routing
Clock Routing
The clock routing structure in LatticeECP/EC devices consists of four Primary Clock lines and a Secondary Clock
network per quadrant. The primary clocks are generated from MUXs located in each quadrant. Figure 2-8 shows
this clock routing. The four secondary clocks are generated from MUXs located in each quadrant as shown in
Figure 2-9. Each slice derives its clock from the primary clock lines, secondary clock lines and routing as shown in
Figure 2-10.
2-8

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