PDF VSC837 Data sheet ( Hoja de datos )

Número de pieza	VSC837
Descripción	3.2Gb/s 68x68 Crosspoint Switch
Fabricantes	Vitesse Semiconductor
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No Preview Available ! www.DataSheet4U.com VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC837 3.2Gb/s 68x68 Crosspoint Switch Features • 68 Input by 68 Output Crosspoint Switch • 3.2Gb/s NRZ Data Bandwidth • 66MHz Multi-Mode Programming Port • TTL/2.5V CMOS Control I/O (3.3V tolerant) • Programmable On-Chip I/O Termination • Input Signal Activity (ISA) Monitoring Function • Integrated Signal Equalization (ISE) for Deterministic Jitter Reduction • Single 2.5V Supply • Differential CML Output Driver • 11W typ/14W max (low drive mode) 13W typ/16W max (high drive mode) • Hard and Soft Power-Down for Unused Channels • High Performance 37.5mm, 480 TBGA Package General Description The VSC837 is a monolithic 68x68 asynchronous crosspoint switch, designed to carry broadband data streams. The non-blocking switch core is programmed through a triple-mode port interface that allows random access programming of each input/output port. A high degree of signal integrity is maintained throughout the chip via fully differential signal paths. The crosspoint function is based on a multiplexer array architecture. Each data output is driven by a 68:1 multiplexer that can be programmed to one and only one of its 68 inputs. The signal path is unregistered and fully asynchronous, so there are no restrictions on the phase, frequency, or signal pattern at each input. Each high-speed output is a fully differential switched current driver with switchable on-die terminations for maximum signal integrity. Data inputs are terminated on die through 100Ω resistors between true and com- plement inputs (see Input Termination section for further detail). A triple-mode programming interface is provided that allows programming commands to be sent as serial data or one of two forms of parallel data. The input-referred mode (burst mode) allows an input port to be routed to all outputs in only 4 program cycles. Core programming can be random for each port address, or multiple program assignments can be queued and issued simultaneously. The programming may be initialized to a “straight-through” configuration (A0 to Y0, A1 to Y1, etc.) using the INITB pin. An activity monitor is provided to allow in-system diagnostics. The activity monitor can observe any high- speed input via an internal 69th multiplexer. Unused channels may be powered down to allow efficient use of the switch in applications that require only a subset of the channels. Power-down can be accomplished in hardware, via dedicated power pins for pairs of input and output channels, or in software by programming individual unused outputs with a disable code. VSC837 Block Diagram A0 2 2 Y0 G52309-0, Rev 3.0 02/16/01 A67 2 2 Y67 µP control © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 1 1 page VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC837 3.2Gb/s 68x68 Crosspoint Switch AC Characteristics Table 1: Data Path Symbol Parameter Min Typ Max Units fRATE Maximum Data Rate — — 3.2 Gb/s tSKW Channel-to-channel delay skew — 300 — ps tPDAY Propagation Delay from an A input to a Y output — 750 — ps tR, tF High-speed input rise/fall times, 20% to 80% — — 150 ps tR, tF tJR tJP High-speed output rise/fall times, 20% to 80% Output added delay jitter, rms(1, 2) Output added delay jitter, peak-to-peak(1, 2) — — 150 ps — — 10 ps — — 40 ps NOTES:(1) Tested on a sample basis only. (2) Broadband (unfiltered) deterministic jitter added to a jitter-free input, 223-1 PRBS data pattern. Table 2: Program Interface Timing Symbol Parameter Min Typ Max Units tsWRB thWRB tpwLW tsCSB Setup time from INCHAN[6:0] or OUTCHAN[6:0] to rising edge of WRB Hold time from rising edge of WRB to INCHAN[6:0] or OUTCHAN[6:0] Pulse width (HIGH or LOW) on LOAD Setup time from CSB to falling edge of LOAD or ALE_SCN in parallel or burst mode, or rising edge of LOAD in serial mode. 3.35 1.45 6.75 0 — — — — — — — — ns ns ns ns thCSB Hold time of CSB rising edge after LOAD or ALE_SCN rising in parallel or burst mode, or falling edge of LOAD in serial mode, or falling edge of CONFIG in any mode. 0 —— ns tpwCFG Pulse width (HIGH or LOW) on CONFIG 6.75 — — ns tsSDIN Setup time from INCHAN0_SDIN to INCHAN1_SCLK rising 1.65 — — ns thSDIN Hold time of INCHAN0_SDIN after INCHAN1_SCLK rising 1.0 — — ns tperSCLK Minimum period of SCLK in serial mode 15 — — ns tsLOAD Setup time from LOAD to INCHAN1_SCLK rising 1.85 — — ns thLOAD Hold time of LOAD after INCHAN1_SCLK rising 0.95 — — ns Setup time from SERIAL rising to INCHAN1_SCLK rising when entering serial tsSERIAL mode or SERIAL falling to LOAD falling when entering parallel mode or SERIAL falling to LOAD rising when entering burst mode. 0.90 — — ns thSERIAL Hold time from INCHAN1_SCLK rising to SERIAL falling when exiting serial mode. 0 —— ns tsBURST Setup time from BURST rising to LOAD rising when entering burst mode or BURST falling to LOAD falling when entering parallel mode. 1.85 — — ns thBURST tdsDOUT tpwINITB tsSCAN Hold time from LOAD rising to BURST falling when exiting burst mode. Delay from INCHAN1_SCLK rising to SDOUT, 20pF load. Pulse width (HIGH or LOW) on INITB Setup time from ALE_SCN to INCHAN1_SCLK rising when starting or completing a serial read-back sequence. 2.45 — — — — 6.20 6.75 — — 1.65 — — ns ns ns ns thSCAN Hold time of ALE_SCN after INCHAN1_SCLK rising when starting or completing a serial read-back sequence. 1.0 — — ns G52309-0, Rev 3.0 02/16/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 5 5 Page VITESSE SEMICONDUCTOR CORPORATION Preliminary Data Sheet VSC837 3.2Gb/s 68x68 Crosspoint Switch Package Pin Descriptions Figure 6: Pinout Diagram—Bottom View Ball grid 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 index OUTCHAN10 OUTCHAN5 A OUTCHAN11 2 6 10 14 18 22 26 30 34 38 42 46 50 54 58 62 66 OUTCHAN6 B OUTCHAN14 OUTCHAN9 C OUTCHAN13 OUTCHAN8 D OUTCHAN12 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 OUTCHAN7 E Inputs [An, ANn] F G VCC H J Dedicated VEE Common VEE (always On) K L M control port N P R T U V W Y AA AB INCHAN2 Inputs [An, ANn] SERIAL INCHAN1_SCLK 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63 67 CSB INCHAN0_SDIN SDOUT INCHAN3 BURST INCHAN4 1 5 9 13 17 21 25 29 33 37 41 45 49 53 57 61 65 INITB AC AD AE AF AG AH AJ G52309-0, Rev 3.0 02/16/01 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: [email protected] Internet: www.vitesse.com Page 11 11 Page

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