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PDF VSC835 Data sheet ( Hoja de datos )

Número de pieza VSC835
Descripción 34x34 Crosspoint Switch
Fabricantes Vitesse Semiconductor 
Logotipo Vitesse Semiconductor Logotipo



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No Preview Available ! VSC835 Hoja de datos, Descripción, Manual

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VITESSE
SEMICONDUCTOR CORPORATION
Datasheet
VSC835
2.5 Gbits/sec
34x34 Crosspoint Switch with Signal Detection
Features
• 34 Input by 34 Output Crosspoint Switch
• 2.5 Gbits/sec. NRZ Data Bandwidth
• TTL Compatible µP Interface
• Differential PECL Data Inputs
• On-chip 50Input Terminations
• 50Source Terminated PECL Output Drivers
• Single 3.3V Supply
• 14W Maximum Power Dissipation
• High Performance 256 BGA Package
General Description
The VSC835 is a monolithic 34x34 asynchronous crosspoint switch, designed to carry broadband data
streams at up to 2.5 Gbit/s. The non-blocking switch core is programmed through a parallel port interface that
allows random access programming of each output port. A high degree of signal integrity is maintained through
the chip through fully differential signal paths.
The crosspoint function is based on a multiplexer tree architecture. Each data output is driven by a 34:1
multiplexer tree that can be programmed to one and only one of its 34 inputs, and each data input can be routed
to multiple outputs. The signal path is unregistered, so no clock is required for the data inputs. The signal path is
asynchronous, so there are no restrictions on the phase, frequency, or signal pattern at each input. Each input
channel and each output channel has an signal monitor function that can be used to identify loss of activity
(LOA). An interrupt pin is provided to signal LOA, after which an external controller can query the chip to
determine the channel(s) on which the fault occurred.
Each output driver is a fully differential switched current driver with on-die back-terminations for maxi-
mum signal integrity. Data inputs are terminated on die through 50 ohm resistors terminated to VTERM.
The parallel interface uses TTL levels, and provides address, data, and control pins that are compatible
with a microprocessor-style interface. The control port provides access to all chip functions, including LOA and
programming. Program buffering is provided to allow multiple program assignments to be queued and issued
simultaneously via a single configure command.
VSC835 Block Diagram
A0 Y0
G52270-0, Rev. 4.1
7/24/00
A33
Control Logic
µP interface
Y33
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 1

1 page




VSC835 pdf
Datasheet
VSC835
VITESSE
SEMICONDUCTOR CORPORATION
2.5 Gbits/sec
34x34 Crosspoint Switch with Signal Detection
Figure 2: Figure 2: Interrupt Timing (Change in Monitor State Registers)
MONCLK
Monitor State
Monitor State Reg
INTB
Figure 3: Figure 3: Interrupt Timing (No change in Monitor State Registers)
MONCLK
Monitor State
Monitor State Reg
INTB
ADR[5:0]
D[5:0]
CSB
WRB
RDB
CONFIG
Figure 4: Figure 4: Program Timing
TsCSB
TsWRB ThWRB
TsCONFIG
G52270-0, Rev. 4.1
7/24/00
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 5

5 Page





VSC835 arduino
Datasheet
VSC835
VITESSE
SEMICONDUCTOR CORPORATION
2.5 Gbits/sec
34x34 Crosspoint Switch with Signal Detection
Figure 7: Pinout Diagram
20 19 18 17 16 15 14 13 12 11 10
9
8
ADR5 ALE
A2 A8 A14
A20
ADR2 MONCLK
76
A26
54
A32
3
ADR1 ADR3
VCOMR
A0 A4 A6 A10 A12 ADR0 ADR4 A16 A18 A22 A24 A28 A30
Y0
Y2
Y4
Y6
Y8
Y10
Y12
Y14
Y16
VCC
VEE
VTERM
Y1
Y5
Y7
Y11
Y13
Y17
Y18
Y20
Y22
BOTTOM VIEW
Y19
Y23
Y24
Y26
Y28
Y25
Y29
Y32
Y30
VHYS
VCOML
D5 D1 WRB
Y31
A1 A5 A7 A11 A13 D4 D2 CSB A17 A21 A23 A27 A29 A33
D3 RDB CONFIG
D0 INTB
A3 A9 A15
A19 A25 A31
BALL
2 1 GRID
INDEX
A
B
C
D
E
Y3
F
G
Y9
H
J
Y15
K
L
Y21
M
N
Y27
P
R
Y33
T
U
V
W
Y
G52270-0, Rev. 4.1
7/24/00
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
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