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PDF MAX1338 Data sheet ( Hoja de datos )
| Número de pieza | MAX1338 | |
| Descripción | Simultaneous-Sampling ADC | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-3151; Rev 1; 7/04
www.DataSheet4U.com
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
General Description
The MAX1338 14-bit, analog-to-digital converter (ADC)
offers four simultaneously sampled, fully differential input
channels, with independent track-and-hold (T/H) circuitry
for each channel. The input channels are individually
software programmable for input ranges of ±10V, ±5V,
±2.5V, and ±1.25V. The input channels feature fault tol-
erance to ±17V. The internal T/H circuits have a 16ns
aperture delay and 100ps aperture-delay matching.
A 14-bit parallel bus provides the conversion result with
a maximum per-channel output rate of 150ksps
(600ksps for all four channels). The MAX1338 has an
on-board oscillator and 2.5V internal reference. An
external clock and/or reference can also be used.
The MAX1338 operates from a +5V supply for analog
inputs and digital core. The device operates from a +2.7V
to +5.25V supply for the digital I/O lines. The MAX1338
features two power-saving modes: standby mode and
shutdown mode. Standby mode allows rapid wake-up
and reduces quiescent current to 4mA (typ), and shut-
down mode reduces sleep current to less than 10µA (typ).
The MAX1338 is available in an 8mm x 8mm x 0.8mm,
56-pin, thin QFN package. The device operates over
the extended -40°C to +85°C temperature range.
Applications
Multiple-Channel Data Recorders
Vibration Analysis
Motor Control: 3-Phase Voltage, Current, and
Power Measurement
Optical Communication Equipment
Features
♦ 150ksps Sample Rate per Channel
♦ All Four Input Channels Simultaneously Sampled
16ns Aperture Delay
100ps Aperture-Delay Matching
♦ Channel-Independent Software-Selectable Input
Range: ±10V, ±5V, ±2.5V, ±1.25V
♦ ±17V Fault-Tolerant Inputs
♦ Dynamic Performance at 10kHz Input
SNR: 77dB
SINAD: 76dB
SFDR: 98dBc
THD: -83dBc
♦ DC Performance
INL: ±2 LSB
DNL: ±1 LSB
Offset Error: ±4 LSB
Gain Error: ±0.1% FSR
♦ 14-Bit Parallel Interface
♦ Internal Clock and Reference Voltage
♦ +5V Analog and Digital Supplies
♦ +2.7V to +5.25V Digital I/O Supply
♦ 56-Pin Thin QFN Package (8mm x 8mm x 0.8mm)
Ordering Information
PART
MAX1338ETN
TEMP RANGE
-40°C to +85°C
*EP = Exposed pad.
PIN-PACKAGE
56 Thin QFN-EP*
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 page  
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
ELECTRICAL CHARACTERISTICS (continued)
(AVDD = DVDD = +5.0V, DRVDD = +3.0V, AGND = DGND = DRGND = 0, INTCLK/EXTCLK = AGND, fCLK = 5MHz, input range =
±10V, REFP2 = REFP1, REFN2 = REFN1, COM1 = COM2, 1.0nF from REFADC to AGND, 1.0µF and 0.1µF from COM1 to AGND,
0.1µF from REFP1 to AGND, 0.1µF from REFN1 to AGND, 1.0µF from REFP1 to REFN1. Typical values are at TA = +25°C. TA = TMIN
to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
TIMING CHARACTERISTICS (Figures 4, 5, and 6)
Internal clock
Time to First Conversion Result
tEOC1 External clock
Time to Subsequent Conversions
tNEXT
Internal clock
External clock
CONVST Pulse-Width Low
CS Pulse Width
RD Pulse-Width Low
RD Pulse-Width High
WR Pulse-Width Low
CS to WR Setup Time
WR to CS Hold Time
CS to RD Setup Time
RD to CS Hold Time
Data Access Time
(RD Low to Valid Data)
tCONVST
tCS
tRDL
tRDH
tWRL
tCTW
tWTC
tCTR
tRTC
Internal clock
External clock
tACC Figure 1
MIN TYP MAX UNITS
2.9 3.2 3.5
µs
16 CLK
Cycles
600 ns
3 CLK
Cycles
0.2
µs
0.1
30 ns
30 ns
30 ns
30 ns
0 ns
0 ns
0 ns
0 ns
30 ns
Bus Relinquish Time
(RD High to D_ High-Z)
tREQ Figure 1
5 30 ns
CLK Rise to End-of-Conversion
(EOC) Rise/Fall Delay
tEOCD
20 ns
CLK Rise to End-of-Last-
Conversion (EOLC) Fall Delay
CONVST Rise to EOLC Fall Delay
EOC Pulse-Width Low
tEOLCD
tCVEOLCD
tEOC
Internal clock
External clock
Wake-Up Time From Standby
Wake-Up Time From Shutdown
All bypass capacitors discharged
20
20
180 200
1
7
5
ns
ns
ns
CLK
Cycle
µs
ns
_______________________________________________________________________________________ 5
5 Page 
14-Bit, 4-Channel, Software-Programmable,
Multiranging, Simultaneous-Sampling ADC
PIN
1, 7, 9, 17,
19
2
3
4
5
6, 8, 14, 16,
18, 20, 28
10
11
12
13
15
21
22
23
24
25
26
27
29
30
31
32
33
34
35
36
37
38
39
40
Pin Description
NAME
AVDD
AIN0+
AIN0-
AIN1+
AIN1-
FUNCTION
Analog Power Input. AVDD is the power input for the analog section of the converter. Connect a
+4.75V to +5.25V power supply to AVDD. Bypass each AVDD to AGND with a 0.1µF capacitor very
close to the device. Bypass AVDD to AGND with a bulk capacitor of at least 4.7µF where power enters
the board. Connect all AVDD pins to the same potential.
Channel 0 Differential Analog Input
Channel 0 Differential Analog Input
Channel 1 Differential Analog Input
Channel 1 Differential Analog Input
AGND Analog Ground. AGND is the power return for AVDD. Connect all AGNDs to the same potential.
AIN2+
AIN2-
AIN3+
AIN3-
INTCLK/
EXTCLK
REFADC
REFP1
REFP2
COM1
COM2
REFN1
REFN2
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
Channel 2 Differential Analog Input
Channel 2 Differential Analog Input
Channel 3 Differential Analog Input
Channel 3 Differential Analog Input
Clock-Select Input. Force INTCLK/EXTCLK high for internal clock mode. Force INTCLK/EXTCLK low
for external clock mode.
ADC Reference Bypass or Input. REFADC is the bypass point for an internally generated reference
voltage. Bypass REFADC with a 1.0nF capacitor to AGND. REFADC can be driven externally by a
precision external voltage reference. See the Reference section and the Typical Operating Circuit.
Positive Differential Reference Bypass Point 1. Connect REFP1 to REFP2.
Positive Differential Reference Bypass Point 2. Connect REFP2 to REFP1. Bypass REFP2 with a 0.1µF
capacitor to AGND. Also bypass REFP2 to REFN2 with a 0.1µF capacitor.
Common-Mode Voltage Bypass Point 1. Connect COM1 to COM2.
Common-Mode Voltage Bypass Point 2. Connect COM2 to COM1. Connect a 1.0µF capacitor from
COM2 to AGND.
Negative Differential Reference Bypass Point 1. Connect REFN1 to REFN2.
Negative Differential Reference Bypass Point 2. Connect REFN2 to REFN1. Bypass REFN2 with a
0.1µF capacitor to AGND. Also bypass REFN2 to REFP2 with a 0.1µF capacitor.
Data Input/Output Bit 0 (LSB)
Data Input/Output Bit 1
Data Input/Output Bit 2
Data Input/Output Bit 3
Data Input/Output Bit 4
Data Input/Output Bit 5
Data Input/Output Bit 6
Data Input/Output Bit 7
Data Output Bit 8
Data Output Bit 9
Data Output Bit 10
Data Output Bit 11
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet MAX1338.PDF ] | |
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