PDF XRT86VL38 Data sheet ( Hoja de datos )

Número de pieza	XRT86VL38
Descripción	OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
Fabricantes	Exar Corporation
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No Preview Available ! www.DataSheet4U.com PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION JULY 2006 REV. P1.0.9 GENERAL DESCRIPTION The XRT86VL38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology (Relayless, Reconfigurable, Redundancy). The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86VL38 provides protection from power failures and hot swapping. The XRT86VL38 contains an integrated DS1/E1/J1 framer and LIU which provide DS1/E1/J1 framing and error accumulation in accordance with ANSI/ITU_T specifications. Each framer has its own framing synchronizer and transmit-receive slip buffers. The slip buffers can be independently enabled or disabled as required and can be configured to frame to the common DS1/E1/J1 signal formats. Each Framer block contains its own Transmit and Receive E1/J1 Framing function. There are 3 Transmit HDLC controllers per channel which encapsulate contents of the Transmit HDLC buffers into LAPD Message frames. There are 3 Receive HDLC controllers per channel which extract the payload content of Receive LAPD Message frames from the incoming E1/J1 data stream and write the contents into the Receive HDLC buffers. Each framer also contains a Transmit and Overhead Data Input port, which permits Data Link Terminal Equipment direct access to the outbound E1/J1 frames. Likewise, a Receive Overhead output data port permits Data Link Terminal Equipment direct access to the Data Link bits of the inbound E1/J1 frames. The XRT86VL38 fully meets all of the latest E1/J1 specifications: ANSI E1.107-1988, ANSI E1.403- 1995, ANSI E1.231-1993, ANSI E1.408-1990, AT&T TR 62411 (12-90) TR54016, and ITU G-703, G.704, G706 and G.733, AT&T Pub. 43801, and ETS 300 011, 300 233, JT G.703, JT G.704, JT G706, I.431. Extensive test and diagnostic functions include Loop- backs, Boundary scan, Pseudo Random bit sequence (PRBS) test pattern generation, Performance Monitor, Bit Error Rate (BER) meter, forced error insertion, and LAPD unchannelized data payload processing according to ITU-T standard Q.921. Applications and Features (next page) FIGURE 1. XRT86VL38 8-CHANNEL DS1 (E1/J1) FRAMER/LIU COMBO Local PCM Highway XRT86VL38 1 of 8-channels Tx Serial Clock Tx Serial Data In Rx Serial Clock Rx Serial Data Out PRBS Generator & Analyser External Data Link Controller Tx Overhead In Rx Overhead Out 2-Frame Slip Buffer Elastic Store Tx Framer 2-Frame Slip Buffer Elastic Store Rx Framer Performance Monitor HDLC/LAPD Controllers Tx LIU Interface LLB LB Rx LIU Interface LIU & Loopback Control TTIP TRING RTIP RRING 8kHz sync OSC Back Plane 1.544-16.384 Mbit/s Signaling & Alarms System (Terminal) Side TxON JTAG DMA Interface Microprocessor Interface INT Memory D[7:0] 3 A[14:0] µP Select Intel/Motorola µP Configuration, Control & Status Monitor 4 WR ALE_AS RD RDY_DTACK 1:2 Turns Ratio 1:1 Turns Ratio RxLOS Line Side Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com 1 page REV. P1.0.9 PRELIMINARY XRT86VL38 OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION 484 BALL - SHRINK THIN BALL GRID ARRAY (BOTTOM VIEW - SEE PIN LIST FOR DESCRIPTION) 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 OOOOOOOOOOOOOOOOOOOOOO A OOOOOOOOOOOOOOOOOOOOOO B OOOOOOOOOOOOOOOOOOOOOO C OOOOOOOOOOOOOOOOOOOOOO D OOOOOOOOOOOOOOOOOOOOOO E OOOOOOOOOOOOOOOOOOOOOO F OOOOOOOOOOOOOOOOOOOOOO G OOOOOOOOOOOOOOOOOOOOOO H OOOOOOOOOOOOOOOOOOOOOO J OOOOOOOOOOOOOOOOOOOOOO K OOOOOOOOOOOOOOOOOOOOOO L OOOOOOOOOOOOOOOOOOOOOO M OOOOOOOOOOOOOOOOOOOOOO N OOOOOOOOOOOOOOOOOOOOOO P OOOOOOOOOOOOOOOOOOOOOO R OOOOOOOOOOOOOOOOOOOOOO T OOOOOOOOOOOOOOOOOOOOOO U OOOOOOOOOOOOOOOOOOOOOO V OOOOOOOOOOOOOOOOOOOOOOW OOOOOOOOOOOOOOOOOOOOOO Y O O O O O O O O O O O O O O O O O O O O O O AA O O O O O O O O O O O O O O O O O O O O O O AB 5 5 Page PRELIMINARY XRT86VL38 REV. P1.0.9 OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION DESCRIPTION OF THE CONTROL REGISTERS - E1 MODE TABLE 1: REGISTER SUMMARY FUNCTION SYMBOL Control Registers (0xn100 - 0xn1FF) Clock and Select Register CSR Line Interface Control Register LICR General Purpose Input/Output Control 0 GPIOCR0 General Purpose Input/Output Control 1 GPIOCR1 Reserved - Framing Select Register FSR Alarm Generation Register AGR Synchronization MUX Register SMR Transmit Signaling and Data Link Select Register TSDLSR Framing Control Register FCR Receive Signaling & Data Link Select Register RSDLSR Receive Signaling Change Register 0 RSCR0 Receive Signaling Change Register 1 RSCR1 Receive Signaling Change Register 2 RSCR2 Receive Signaling Change Register 3 RSCR3 Receive National Bits Register RNBR Receive Extra Bits Register REBR Data Link Control Register 1 DLCR1 Transmit Data Link Byte Count Register 1 TDLBCR1 Receive Data Link Byte Count Register 1 RDLBCR1 Slip Buffer Control Register SBCR FIFO Latency Register FIFOLR DMA 0 (Write) Configuration Register D0WCR DMA 1 (Read) Configuration Register D1RCR Interrupt Control Register ICR LAPD Select Register LAPDSR Reserved - T1 mode only - Performance Report Control Register PRCR Gapped Clock Control Register GCCR Transmit Interface Control Register TICR HEX 0xn100 0xn101 0x0102 0x4102 0xn103 - 0xn106 0xn107 0xn108 0xn109 0xn10A 0xn10B 0xn10C 0xn10D 0xn10E 0xn10F 0xn110 0xn111 0xn112 0xn113 0xn114 0xn115 0xn116 0xn117 0xn118 0xn119 0xn11A 0xn11B 0xn11C 0xn11D 0xn11E 0xn120 6 11 Page

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