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PDF XRT86VL34 Data sheet ( Hoja de datos )

Número de pieza XRT86VL34
Descripción QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
Fabricantes Exar Corporation 
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PRELIMINARY
XRT86VL34
JULY 2005
QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. P1.0.5
GENERAL DESCRIPTION
The XRT86VL34 is a four-channel 1.544 Mbit/s or
2.048 Mbit/s DS1/E1/J1 framer and LIU integrated
solution featuring R3 technology (Relayless,
Reconfigurable, Redundancy). The physical
interface is optimized with internal impedance, and
with the patented pad structure, the XRT86VL34
provides protection from power failures and hot
swapping.
The XRT86VL34 contains an integrated DS1/E1/J1
framer and LIU which provide DS1/E1/J1 framing and
error accumulation in accordance with ANSI/ITU_T
specifications. Each framer has its own framing
synchronizer and transmit-receive slip buffers. The
slip buffers can be independently enabled or disabled
as required and can be configured to frame to the
common DS1/E1/J1 signal formats.
Each Framer block contains its own Transmit and
Receive T1/E1/J1 Framing function. There are 3
Transmit HDLC controllers per channel which
encapsulate contents of the Transmit HDLC buffers
into LAPD Message frames. There are 3 Receive
HDLC controllers per channel which extract the
payload content of Receive LAPD Message frames
from the incoming T1/E1/J1 data stream and write the
contents into the Receive HDLC buffers. Each framer
also contains a Transmit and Overhead Data Input
port, which permits Data Link Terminal Equipment
direct access to the outbound T1/E1/J1 frames.
Likewise, a Receive Overhead output data port
permits Data Link Terminal Equipment direct access
to the Data Link bits of the inbound T1/E1/J1 frames.
The XRT86VL34 fully meets all of the latest T1/E1/J1
specifications: ANSI T1/E1.107-1988, ANSI T1/
E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/
E1.408-1990, AT&T TR 62411 (12-90) TR54016, and
ITU G-703, G.704, G706 and G.733, AT&T Pub.
43801, and ETS 300 011, 300 233, JT G.703, JT
G.704, JT G706, I.431. Extensive test and diagnostic
functions include Loop-backs, Boundary scan,
Pseudo Random bit sequence (PRBS) test pattern
generation, Performance Monitor, Bit Error Rate
(BER) meter, forced error insertion, and LAPD
unchannelized data payload processing according to
ITU-T standard Q.921.
Applications and Features (next page)
FIGURE 1. XRT86VL34 4-CHANNEL DS1 (T1/E1/J1) FRAMER/LIU COMBO
Local PCM
Highway
XRT86VL34
1 of 4-channels
Tx Serial
Clock
Tx Serial
Data In
Rx Serial
Clock
Rx Serial
Data Out
PRBS
Generator &
Analyser
External Data
Link Controller
Tx Overhead In
Rx Overhead Out
2-Frame
Slip Buffer
Elastic Store
Tx Framer
2-Frame
Slip Buffer
Elastic Store
Rx Framer
Performance
Monitor
HDLC/LAPD
Controllers
Tx LIU
Interface
LLB LB
Rx LIU
Interface
LIU &
Loopback
Control
TTIP
TRING
RTIP
RRING
8kHz sync
OSC
Back Plane
1.544-16.384 Mbit/s
Signaling &
Alarms
System (Terminal) Side
TxON
JTAG
DMA
Interface
Microprocessor
Interface
INT
Memory
D[7:0]
3
A[13:0]
µP
Select
Intel/Motorola µP
Configuration, Control &
Status Monitor
4 WR
ALE_AS
RD
RDY_DTACK
1:2 Turns Ratio
1:1 Turns Ratio
RxLOS
Line Side
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com

1 page




XRT86VL34 pdf
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REV. P1.0.5
PRELIMINARY
XRT86VL34
QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
LIST OF FIGURES
Figure 1.: XRT86VL34 4-channel DS1 (T1/E1/J1) Framer/LIU Combo ............................................................................. 1
II

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XRT86VL34 arduino
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REV. P1.0.5
PRELIMINARY
XRT86VL34
QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
TABLE 1: REGISTER SUMMARY
FUNCTION
SYMBOL
HEX
Receive Channel Control Register 0-31
RCCR 0-31
0xn360 -
0xn37F
Receive User Code Register 0-31
RUCR 0-31
0xn380 -
0xn39F
Receive Signaling Control Register 0-31
RSCR 0-31
0xn3A0 -
0xn3BF
Receive Substitution Signaling Register 0-31
RSSR 0-31
0xn3C0 -
0xn3DF
Receive Signaling Array (0xn500 - 0xn51F)
Receive Signaling Array Register 0
RSAR0-31
0xn500 -
0xn51F
LAPDn Buffer 0
LAPD Buffer 0 Control Register
LAPDBCR0
0xn600 -
0xn660
LAPDn Buffer 1
LAPD Buffer 1 Control Register
LAPDBCR1
0xn700 -
0xn760
Performance Monitor
Receive Line Code Violation Counter: MSB
RLCVCU
0xn900
Receive Line Code Violation Counter: LSB
RLCVCL
0xn901
Receive Frame Alignment Error Counter: MSB
RFAECU
0xn902
Receive Frame Alignment Error Counter: LSB
RFAECL
0xn903
Receive Severely Errored Frame Counter
RSEFC
0xn904
Receive Synchronization Bit (CRC-6 (T1) CRC-4 (E1) Block) Error
Counter: MSB
RSBBECU
0xn905
Receive Synchronization Bit (CRC-6 (T1) CRC-4 (E1) Block) Error
Counter: LSB
RSBBECL
0xn906
Receive Far-End Block Error Counter: MSB
RFEBECU
0xn907
Receive Far-End Block Error Counter: LSB
RFEBECL
0xn908
Receive Slip Counter
RSC
0xn909
Receive Loss of Frame Counter
RLFC
0xn90A
Receive Change of Frame Alignment Counter
RCFAC
0xn90B
LAPD Frame Check Sequence Error counter 1
LFCSEC1
0xn90C
PRBS bit Error Counter: MSB
PBECU
0xn90D
PRBS bit Error Counter: LSB
PBECL
0xn90E
Transmit Slip Counter
TSC
0xn90F
6

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