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PDF XRT86L30 Data sheet ( Hoja de datos )

Número de pieza XRT86L30
Descripción SINGLE T1/E1/J1 FRAMER/LIU COMBO
Fabricantes Exar Corporation　
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PRELIMINARY
XRT86L30
PRELIMINARY
MAY 2004
SINGLE T1/E1/J1 FRAMER/LIU COMBO
REV. P1.0.1
GENERAL DESCRIPTION
The XRT86L30 is a single channel 1.544 Mbit/s or
2.048 Mbit/s DS1/E1/J1 framer and LIU integrated
solution featuring R3 technology (Relayless, Recon-
figurable, Redundancy). The physical interface is op-
timized with internal impedance, and with the patent-
ed pad structure, the XRT86L30 provides protection
from power failures and hot swapping.
The XRT86L30 contains an integrated DS1/E1/J1
framer and LIU which provide DS1/E1/J1 framing and
error accumulation in accordance with ANSI/ITU_T
specifications. The framer has a framing synchronizer
and transmit-receive slip buffers. The slip buffers can
be independently enabled or disabled as required
and can be configured to frame to the common DS1/
E1/J1 signal formats.
The Framer block contains a Transmit and Receive
T1/E1/J1 Framing function. There are 3 Transmit
HDLC controllers which encapsulate contents of the
Transmit HDLC buffers into LAPD Message frames.
There are 3 Receive HDLC controllers which extract
the payload content of Receive LAPD Message
frames from the incoming T1/E1/J1 data stream and
write the contents into the Receive HDLC buffers.
The framer also contains a Transmit and Overhead
Data Input port, which permits Data Link Terminal
Equipment direct access to the outbound T1/E1/J1
frames. Likewise, a Receive Overhead output data
port permits Data Link Terminal Equipment direct ac-
cess to the Data Link bits of the inbound T1/E1/J1
frames.
The XRT86L30 fully meets all of the latest T1/E1/J1
specifications: ANSI T1/E1.107-1988, ANSI T1/
E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/
E1.408-1990, AT&T TR 62411 (12-90) TR54016, and
ITU G-703, G.704, G706 and G.733, AT&T Pub.
43801, and ETS 300 011, 300 233, JT G.703, JT
G.704, JT G706, I.431. Extensive test and diagnostic
functions include Loop-backs, Boundary scan, Pseu-
do Random bit sequence (PRBS) test pattern gener-
ation, Performance Monitor, Bit Error Rate (BER)
meter, forced error insertion, and LAPD unchannel-
ized data payload processing according to ITU-T
standard Q.921.
Applications and Features (next page)
FIGURE 1. XRT86L30 1-CHANNEL DS1 (T1/E1/J1) FRAMER/LIU COMBO
Local PCM
Highway
XRT86L30
External Data
Link Controller
Tx Overhead In
Rx Overhead Out
Tx Serial
Clock
Rx Serial
Clock
8kHz sync
OSC
Back Plane
1.544-16.384 Mbit/s
Tx Serial
Data In
Rx Serial
Data Out
PRBS
Generator &
Analyser
Signaling &
Alarms
System (Terminal) Side
TxON
2-Frame
Slip Buffer
Elastic Store
Tx Framer
2-Frame
Slip Buffer
Elastic Store
Rx Framer
Performance
Monitor
HDLC/LAPD
Controllers
Tx LIU
Interface
LLB LB
Rx LIU
Interface
LIU &
Loopback
Control
TTIP
TRING
RTIP
RRING
JTAG
DMA
Interface
Microprocessor
Interface
INT
Memory
D[7:0]
3
A[11:0]
µP
Select
Intel/Motorola µP
Configuration, Control &
Status Monitor
4 WR
ALE_AS
RD
RDY_DTACK
1:2 Turns Ratio
1:1 Turns Ratio
RxLOS
Line Side
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

1 page




XRT86L30 pdf
PRELIMINARY
SINGLE T1/E1/J1 FRAMER/LIU COMBO
XRT86L30
REV. P1.0.1
6.7.9 COMMAND OR RESPONSE BIT (C/R) ...................................................................................................................... 170
6.7.10 SERVICE ACCESS POINT IDENTIFIER (SAPI) ...................................................................................................... 170
6.7.11 TERMINAL ENDPOINT IDENTIFIER (TEI) ............................................................................................................... 170
6.7.12 CONTROL FIELD ...................................................................................................................................................... 170
6.7.13 FRAME CHECK SEQUENCE (FCS) FIELD ............................................................................................................. 170
6.7.14 TRANSPARENCY (ZERO STUFFING) ..................................................................................................................... 171
6.8 TRANSMIT SLC®96 DATA LINK CONTROLLER .......................................................................................... 172
6.9 D/E TIME SLOT TRANSMIT HDLC CONTROLLER BLOCK V5.1 OR V5.2 INTERFACE ............................ 173
6.10 AUTOMATIC PERFORMANCE REPORT (APR) .......................................................................................... 173
6.10.1 BIT VALUE INTERPRETATION ............................................................................................................................... 173
7.0 OVERHEAD INTERFACE BLOCK ...................................................................................................... 175
7.1 DS1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK .......................................................................... 175
7.1.1 DESCRIPTION OF THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK .............................................. 175
7.1.2 CONFIGURE THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE FACILITY DATA
LINK (FDL) BITS IN ESF FRAMING FORMAT MODE ............................................................................................... 175
7.1.3 CONFIGURE THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE SIGNALING
FRAMING (FS) BITS IN N OR SLC®96 FRAMING FORMAT MODE ........................................................................ 177
7.1.4 CONFIGURE THE DS1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE REMOTE SIG-
NALING (R) BITS IN T1DM FRAMING FORMAT MODE ........................................................................................... 178
7.2 DS1 RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK ......................................................................... 178
7.2.1 DESCRIPTION OF THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK ............................................. 179
7.2.2 CONFIGURE THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS DESTINATION OF THE FACILITY
DATA LINK (FDL) BITS IN ESF FRAMING FORMAT MODE .................................................................................... 179
7.2.3 CONFIGURE THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS DESTINATION OF THE SIGNALING
FRAMING (FS) BITS IN N OR SLC®96 FRAMING FORMAT MODE ........................................................................ 180
7.2.4 CONFIGURE THE DS1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS DESTINATION OF THE REMOTE
SIGNALING (R) BITS IN T1DM FRAMING FORMAT MODE ..................................................................................... 181
7.3 E1 OVERHEAD INTERFACE BLOCK ............................................................................................................ 182
7.4 E1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK ............................................................................. 182
7.4.1 DESCRIPTION OF THE E1 TRANSMIT OVERHEAD INPUT INTERFACE BLOCK ................................................. 182
7.4.2 CONFIGURE THE E1 TRANSMIT OVERHEAD INPUT INTERFACE MODULE AS SOURCE OF THE NATIONAL BIT SE-
QUENCE IN E1 FRAMING FORMAT MODE .............................................................................................................. 183
7.5 E1 RECEIVE OVERHEAD INTERFACE ......................................................................................................... 185
7.5.1 DESCRIPTION OF THE E1 RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK ............................................... 185
7.5.2 CONFIGURE THE E1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS SOURCE OF THE NATIONAL BIT
SEQUENCE IN E1 FRAMING FORMAT MODE .......................................................................................................... 186
8.0 LIU TRANSMIT PATH ......................................................................................................................... 188
8.1 TRANSMIT DIAGNOSTIC FEATURES ........................................................................................................... 188
8.1.1 TAOS (TRANSMIT ALL ONES) .................................................................................................................................. 188
8.1.2 ATAOS (AUTOMATIC TRANSMIT ALL ONES) ......................................................................................................... 189
8.1.3 NETWORK LOOP UP CODE ...................................................................................................................................... 189
8.1.4 NETWORK LOOP DOWN CODE ............................................................................................................................... 189
8.1.5 QRSS GENERATION .................................................................................................................................................. 190
8.2 T1 LONG HAUL LINE BUILD OUT (LBO) ...................................................................................................... 190
8.3 T1 SHORT HAUL LINE BUILD OUT (LBO) .................................................................................................... 191
8.3.1 ARBITRARY PULSE GENERATOR ........................................................................................................................... 191
8.3.2 DMO (DIGITAL MONITOR OUTPUT) ......................................................................................................................... 192
8.3.3 TRANSMIT JITTER ATTENUATOR ........................................................................................................................... 192
8.4 LINE TERMINATION (TTIP/TRING) ................................................................................................................ 193
9.0 LIU RECEIVE PATH ............................................................................................................................ 194
9.1 LINE TERMINATION (RTIP/RRING) ............................................................................................................... 194
9.1.1 CASE 1: INTERNAL TERMINATION .......................................................................................................................... 194
9.1.2 CASE 2: INTERNAL TERMINATION WITH ONE EXTERNAL FIXED RESISTOR FOR ALL MODES .................... 194
9.1.3 EQUALIZER CONTROL ............................................................................................................................................. 195
9.1.4 CABLE LOSS INDICATOR ......................................................................................................................................... 195
9.2 RECEIVE SENSITIVITY ................................................................................................................................... 196
9.2.1 AIS (ALARM INDICATION SIGNAL) .......................................................................................................................... 196
9.2.2 NLCD (NETWORK LOOP CODE DETECTION) ......................................................................................................... 196
9.2.3 FLSD (FIFO LIMIT STATUS DETECTION) ................................................................................................................ 197
9.2.4 RECEIVE JITTER ATTENUATOR .............................................................................................................................. 197
9.2.5 RXMUTE (RECEIVER LOS WITH DATA MUTING) ................................................................................................... 197
10.0 THE E1 TRANSMIT/RECEIVE FRAMER .......................................................................................... 199
10.1 DESCRIPTION OF THE TRANSMIT/RECEIVE PAYLOAD DATA INPUT INTERFACE BLOCK ................ 199
10.1.1 BRIEF DISCUSSION OF THE TRANSMIT/RECEIVE PAYLOAD DATA INPUT INTERFACE BLOCK OPERATING AT
II

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XRT86L30 arduino
REV. P1.0.1
PRELIMINARY
XRT86L30
SINGLE T1/E1/J1 FRAMER/LIU COMBO
LIST OF TABLES
Table 2:: Selecting the Microprocessor Interface Mode .................................................................................................. 24
Table 3:: XRT86L30 Microprocessor Interface Signals that exhibit constant roles in both Intel and Motorola Modes .... 25
Table 4:: Intel mode: Microprocessor Interface Signals ................................................................................................... 25
Table 5:: Motorola Mode: Microprocessor Interface Signals ........................................................................................... 26
Table 6:: Intel Microprocessor Interface Timing Specifications ....................................................................................... 28
Table 7:: Intel Microprocessor Interface Timing Specifications ....................................................................................... 30
Table 8:: Motorola 68K Microprocessor Interface Timing Specifications ......................................................................... 31
Table 9:: XRT86L30 Framer/LIU Register Map ............................................................................................................... 33
Table 10:: Register Summary .......................................................................................................................................... 34
Table 11:: Clock Select Register E1 Mode ...................................................................................................................... 40
Table 12:: Line Interface Control Register T1 Mode ........................................................................................................ 41
Table 13:: General Purpose Input/Output 0 Control Register .......................................................................................... 42
Table 14:: Framing Select Register-E1 Mode .................................................................................................................. 43
Table 15:: Framing Select Register-T1 Mode .................................................................................................................. 44
Table 16:: Alarm Generation Register - E1 Mode ............................................................................................................ 45
Table 17:: Alarm Generation Register -T1 Mode ............................................................................................................. 46
Table 18:: Synchronization MUX Register - E1 Mode ..................................................................................................... 47
Table 19:: Synchronization MUX Register - T1 Mode ..................................................................................................... 48
Table 20:: Transmit Signaling and Data Link Select Register - E1 Mode ........................................................................ 49
Table 21:: Transmit Signaling and Data Link Select Register - T1 Mode ........................................................................ 50
Table 22:: Framing Control Register E1 Mode ................................................................................................................ 51
Table 23:: Framing Control Register T1 Mode ................................................................................................................ 52
Table 24:: Receive Signaling & Data Link Select Register - E1 Mode ............................................................................ 53
Table 25:: Receive Signaling & Data Link Select Register (RS&DLSR) T1 Mode .......................................................... 54
Table 26:: Signaling Change Register 0 - T1 Mode ......................................................................................................... 54
Table 27:: Signaling Change Register 1 .......................................................................................................................... 55
Table 28:: Signaling Change Register 2 .......................................................................................................................... 55
Table 29:: Signaling Change Register 3 .......................................................................................................................... 56
Table 30:: Receive National Bits Register ....................................................................................................................... 56
Table 31:: Receive Extra Bits Register ............................................................................................................................ 57
Table 32:: Data Link Control Register .............................................................................................................................. 58
Table 33:: Transmit Data Link Byte Count Register ........................................................................................................ 59
Table 34:: Receive Data Link Byte Count Register ......................................................................................................... 59
Table 35:: Slip Buffer Control Register ............................................................................................................................ 60
Table 36:: FIFO Latency Register .................................................................................................................................... 60
Table 37:: DMA 0 (Write) Configuration Register ............................................................................................................ 61
Table 38:: DMA 1 (Read) Configuration Register ............................................................................................................ 62
Table 39:: Interrupt Control Register ............................................................................................................................... 62
Table 40:: LAPD Select Register ..................................................................................................................................... 63
Table 41:: Customer Installation Alarm Generation Register .......................................................................................... 63
Table 42:: Performance Report Control Register ............................................................................................................ 64
Table 43:: Gapped Clock Control Register ...................................................................................................................... 64
Table 44:: Gapped Clock Control Register ...................................................................................................................... 65
Table 45:: Transmit Interface Control Register - E1 Mode .............................................................................................. 66
Table 46:: Transmit Interface Control Register - T1 Mode .............................................................................................. 67
Table 47:: Receive Interface Control Register (RICR) - E1 Mode ................................................................................... 68
Table 48:: Receive Interface Control Register (RICR) - T1 Mode ................................................................................... 69
Table 49:: DS1 Test Register .......................................................................................................................................... 70
Table 50:: Loopback Code Control Register .................................................................................................................... 71
Table 51:: Transmit Loopback Coder Register ................................................................................................................ 71
Table 52:: Receive Loopback Activation Code Register .................................................................................................. 72
Table 53:: Receive Loopback Deactivation Code Register ............................................................................................. 72
Table 54:: Transmit Sa Select Register ........................................................................................................................... 73
Table 55:: Transmit Sa Auto Control Register 1 .............................................................................................................. 74
Table 56:: Conditions on Receive side When TSACR1 bits Are enabled ........................................................................ 74
Table 57:: Transmit Sa Auto Control Register 2 .............................................................................................................. 75
Table 58:: Conditions on Receive side When TSACR1 bits enabled .............................................................................. 75
Table 59:: Transmit Sa4 Register .................................................................................................................................... 75
A

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