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PDF ICS85354 Data sheet ( Hoja de datos )
| Número de pieza | ICS85354 | |
| Descripción | DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER | |
| Fabricantes | ICST | |
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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS85354
DUAL 2:1/1:2
DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER
GENERAL DESCRIPTION
ICS
The ICS85354 is a 2:1/1:2 Multiplexer and a mem-
ber of the HiPerClockSTM family of high perfor-
HiPerClockS™ mance clock solutions from ICS.The 2:1 Multiplexer
allows one of 2 inputs to be selected onto one out-
put pin and the 1:2 MUX switches one input to one
of two outputs. This device may be useful for multiplexing multi-
rate Ethernet Phys which have 100Mbit and 1000Mbit transmit/
receive pairs onto an optical SFP module which has a single
trasmit/receive pair. Please refer to the Application Block dia-
gram on page 2 of the data sheet.
The ICS85354 is optimized for applications requiring very high
performance and has a maximum operating frequency in excess
of 2GHz.The device is packaged in a small, 3mm x 3mm VFQFN
package, making it ideal for use on space-constrained boards.
FEATURES
• Dual 2:1/1:2 MUX
• 3 LVPECL outputs
• 3 differential clock inputs
• CLKx pair can accept the following differential input levels:
LVPECL, LVDS, CML
• Maximum output frequency: 3GHz
• Part-to-part skew: 85ps (typical)
• Additive jitter, RMS: 0.03ps (typical)
• Propagation delay: 330ps (typical)
• LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.465V, VEE = 0V
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.465V to -2.375V
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
CLK_SELA
CLKA0
nCLKA0
CLKA1
nCLKA1
CLKB
nCLKB
CLK_SELB
PIN ASSIGNMENT
0
QA
nQA
1
QB0
nQB0
QB1
nQB1
16 15 14 13
QB0 1
12 CLKA0
nQB0 2
11 nCLKA0
QB1 3
10 CLKA1
nQB1 4
9 nCLKA1
5678
ICS85354
16-Lead VFQFN
3mm x 3mm x 0.95 package body
K Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
85354AK
www.icst.com/products/hiperclocks.html
REV. B JUNE 8, 2004
1
1 page  
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS85354
DUAL 2:1/1:2
DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
Negative Supply Voltage, VEE
Inputs, VI (LVPECL mode)
Inputs, V (ECL mode)
I
Outputs, I
O
Continuous Current
Surge Current
Operating Temperature Range, TA
Storage Temperature, TSTG
Package Thermal Impedance, θJA
(Junction-to-Ambient)
4.6V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute
-4.6V (ECL mode, VCC = 0)
Maximum Ratings may cause permanent damage
-0.5V to VCC + 0.5 V
to the device. These ratings are stress specifi-
0.5V to V - 0.5V
EE
cations only. Functional operation of product at
these conditions or any conditions beyond those
50mA
100mA
-40°C to +85°C
listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may
-65°C to 150°C
affect product reliability.
51.5°C/W (0 lfpm)
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375V TO 3.465V, VEE = 0V OR VCC = 0V, VEE = -3.465V TO -2.375V
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VCC Positive Supply Voltage
3.135
3.3
3.465
V
2.375
2.5
2.625
V
IEE Power Supply Current
38 mA
TABLE
4B.
LVCMOS
/
LVTTL
DC
CHARACTERISTICS,
V
CC
=
2.375V
TO
3.465V
Symbol Parameter
Test Conditions
VIH Input High Voltage CLK_SELx
VIL Input Low Voltage CLK_SELx
IIH
Input High Current
CLK_SELA,
CLK_SELB
IIL
Input Low Current
CLK_SELA,
CLK_SELB
VCC = 2.5V or 3.3V
VCC = 2.5V or 3.3V
VCC = VIN = 3.465V,
VCC = VIN = 2.625V
VCC = 3.465
2.625V, VIN = 0V
Minimum
2
0
-150
Typical
Maximum
VCC + 0.3
0.8
150
Units
V
V
µA
µA
85354AK
www.icst.com/products/hiperclocks.html
5
REV. B JUNE 8, 2004
5 Page 
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS85354
DUAL 2:1/1:2
DIFFERENTIAL -TO-LVPECL/ECL MULTIPLEXER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 4A to 4E show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in Figure 4A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
Zo = 50 Ohm
Zo = 50 Ohm
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
3.3V
CLK
nCLK HiPerClockS
Input
R1 R2
50 50
3.3V
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
3.3V
CLK
nCLK HiPerClockS
Input
R1 R2
50 50
R3
50
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
3.3V
R3 R4
125 125
3.3V
CLK
nCLK HiPerClockS
Input
R1 R2
84 84
3.3V
LVDS_Driv er
Zo = 50 Ohm
Zo = 50 Ohm
R1
100
3.3V
CLK
nCLK Receiv er
FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
LVPECL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
R3 R4
125 125
C1
C2
R5
100 - 200
R6
100 - 200
R1 R2
84 84
3.3V
CLK
nCLK HiPerClockS
Input
R5,R6 locate near the driver pin.
FIGURE 4E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
85354AK
www.icst.com/products/hiperclocks.html
11
REV. B JUNE 8, 2004
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ICS85354.PDF ] | |
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