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PDF ICS8535-21 Data sheet ( Hoja de datos )
| Número de pieza | ICS8535-21 | |
| Descripción | LVPECL FANOUT BUFFER | |
| Fabricantes | ICST | |
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Integrated
Circuit
Systems, Inc.
ICS8535-21
LOW SKEW, 1-TO-2
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
ICS
The ICS8535-21 is a low skew, high performance
1-to-2 LVCMOS/LVTTL-to-3.3V LVPECL fanout
HiPerClockS™ buffer and a member of the HiPerClockS™ fam-
ily of High Performance Clock Solutions from
ICS. The ICS8535-21 has two single-ended clock
inputs. The single-ended clock input accepts LVCMOS or
LVTTL input levels and translate them to 3.3V LVPECL lev-
els. The clock enable is internally synchronized to eliminate
runt clock pulses on the output during asynchronous asser-
tion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8535-21 ideal for those applications demand-
ing well defined performance and repeatability.
FEATURES
• 2 differential 3.3V LVPECL outputs
• Selectable CLK0 or CLK1 inputs for redundant
and multiple frequency fanout applications
• CLK0 or CLK1 can accept the following input levels:
LVCMOS or LVTTL
• Maximum output frequency: 266MHz
• Translates LVCMOS and LVTTL levels to
3.3V LVPECL levels
• Output skew: 20ps (maximum)
• Part-to-part skew: 300ps (maximum)
• Propagation delay: 1.6ns (maximum)
• Additive phase jitter, RMS: 0.03ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
CLK_EN
CLK0
CLK1
CLK_SEL
0
1
D
Q
LE
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
VEE
CLK_EN
CLK_SEL
CLK0
VEE
CLK1
VCC
1
2
3
4
5
6
7
14 VCC
13 Q0
12 nQ0
11 nc
10 Q1
9 nQ1
8 VCC
ICS8535-21
14-Lead TSSOP
4.4mm x 5.0mm x 0.92mm body package
G Package
Top View
8535AG-21
www.icst.com/products/hiperclocks.html
1
REV. A OCTOBER 20, 2004
1 page  
Integrated
Circuit
Systems, Inc.
ICS8535-21
LOW SKEW, 1-TO-2
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
fMAX
tPD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 5
IJ 266MHz
1.0
266
1.6
20
tsk(pp) Part-to-Part Skew; NOTE 3, 5
tjit
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section, NOTE 4
156.25MHz @ Integration
Range: 12KHz - 20MHz
0.03
tR/tF Output Rise/Fall Time
odc Output Duty Cycle
20% to 80% @ 50MHz
IJ 200MHz
300
45
All parameters measured at IJ 266MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the VCC/2 of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: Driving only one input clock.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
300
600
55
Units
MHz
ns
ps
ps
ps
ps
%
8535AG-21
www.icst.com/products/hiperclocks.html
5
REV. A OCTOBER 20, 2004
5 Page 
Integrated
Circuit
Systems, Inc.
ICS8535-21
LOW SKEW, 1-TO-2
LVCMOS/LVTTL-TO-3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
V
CC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination voltage of V - 2V.
CC
• For logic high, V = V = V – 0.9V
OUT
OH_MAX
CC_MAX
(V - V ) = 0.9V
CC_MAX OH_MAX
• For logic low, V = V = V – 1.7V
OUT
OL_MAX
CC_MAX
(V - V ) = 1.7V
CC_MAX OL_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
– (V - 2V))/R ] * (V
- V ) = [(2V - (V
- V ))/R ] * (V
-V )=
OH_MAX
CC_MAX
L CC_MAX OH_MAX
CC_MAX OH_MAX
L
CC_MAX OH_MAX
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V – (V - 2V))/R ] * (V - V ) = [(2V - (V
- V ))/R ] * (V - V ) =
OL_MAX
CC_MAX
L CC_MAX OL_MAX
CC_MAX OL_MAX
L
CC_MAX OL_MAX
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
8535AG-21
www.icst.com/products/hiperclocks.html
11
REV. A OCTOBER 20, 2004
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ICS8535-21.PDF ] | |
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