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PDF ICS8535-11 Data sheet ( Hoja de datos )

Número de pieza ICS8535-11
Descripción LVPECL FANOUT BUFFER
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No Preview Available ! ICS8535-11 Hoja de datos, Descripción, Manual

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Integrated
Circuit
Systems, Inc.
ICS8535-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS8535-11 is a low skew, high performance
,&6 1-to-4 3.3V Crystal Oscillator/LVCMOS-to-3.3V
HiPerClockSLVPECL fanout buffer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS. The ICS8535-11 has select-
able single ended clock or crystal inputs. The single ended
clock input accepts LVCMOS or LVTTL input levels and
translate them to 3.3V LVPECL levels. The output enable is
internally synchronized to eliminate runt pulses on the out-
puts during asynchronous assertion/deassertion of the clock
enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8535-11 ideal for those applications demand-
ing well defined performance and repeatability.
FEATURES
4 differential 3.3V LVPECL outputs
Selectable CLK or crystal inputs
CLK can accept the following input levels: LVCMOS, LVTTL
Maximum output frequency up to 266MHz
Output skew: 35ps (maximum)
Part-to-part skew: 150ps (maximum)
Propagation delay: 2.4ns (maximum)
3.3V operating supply
0°C to 70°C ambient operating temperature
Industrial Temperature information available upon request
BLOCK DIAGRAM
CLK_EN
CLK
XTAL1
XTAL2
CLK_SEL
0
1
D
Q
LE
PIN ASSIGNMENT
VEE
CLK_EN
1
2
20 Q0
19 nQ0
CLK_SEL 3
CLK 4
18 V
CC
17 Q1
Q0
nQ0
nc 5
XTAL1 6
16 nQ1
15 Q2
Q1
nQ1
XTAL2
nc
nc
7
8
9
14 nQ2
13 VCC
12 Q3
Q2 VCC 10 11 nQ3
nQ2
ICS8535-11
Q3 20-Lead TSSOP
nQ3 6.5mm x 4.4mm x 0.92mm Package Body
G Package
Top View
8535AG-11
www.icst.com/products/hiperclocks.html
1
REV. B JULY 27, 2001

1 page




ICS8535-11 pdf
Integrated
Circuit
Systems, Inc.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Mode of Oscillation
Frequency Tolerance
Frequency Stability
Drive Level
Equivalent Series Resistance (ESR)
Shunt Capacitance
Series Pin Inductance
Operating Temperature Range
Aging
Frequency Range
ICS8535-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
Test Conditions
Per year @ 25°C
Minimum Typical Maximum
Fundamental
-50 50
-100
100
0.1
50 80
7
37
0 70
-5 5
14 25
Units
ppm
ppm
mW
pF
nH
°C
ppm
MHz
TABLE 6. AC CHARACTERISTICS, VCC=3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
fMAX
tPD
tsk(o)
Maximum Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 5
ƒ266MHz
1.0
25
266
2.4
35
tsk(pp) Part-to-Part skew; NOTE 3, 5
150
tR Output Rise Time
20% to 80% @ 50MHz
300
tF Output Fall Time
20% to 80% @ 50MHz
300
odc Output Duty Cycle; NOTE 4
48
50
700
700
52
oscTOL Crystal Oscillator Tollerance
1000
All parameters measured at 266MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the 50% point of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: Measured using CLK input. For XTAL input, refer to Application Note.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
ns
ps
ps
ps
ps
%
ppm
8535AG-11
www.icst.com/products/hiperclocks.html
5
REV. B JULY 27, 2001

5 Page





ICS8535-11 arduino
Integrated
Circuit
Systems, Inc.
ICS8535-11
LOW SKEW, 1-TO-4, CRYSTAL OSCILLATOR/
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 10.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 10 - LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50load, and a termination
voltage of V - 2V.
CC
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V (V - 2V))/R ] * (V - V )
OH_MAX
CC_MAX
L CC_MAX OH_MAX
Pd_L = [(V (V - 2V))/R ] * (V - V )
OL_MAX
CC_MAX
L CC_MAX OL_MAX
For logic high, V = V = V – 1.0V
OUT
OH_MAX
CC_MAX
Using V
= 3.465, this results in V
= 2.465V
CC_MAX
OH_MAX
For logic low, V = V = V – 1.7V
OUT
OL_MAX
CC_MAX
Using V = 3.465, this results in V = 1.765V
CC_MAX
OL_MAX
Pd_H = [(2.465V - (3.465V - 2V))/50] * (3.465V - 2.465V) = 20mW
Pd_L = [(1.765V - (3.465V - 2V))/50] * (3.465V - 1.765V) = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
8535AG-11
www.icst.com/products/hiperclocks.html
11
REV. B JULY 27, 2001

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