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PDF ICS8535-01 Data sheet ( Hoja de datos )
| Número de pieza | ICS8535-01 | |
| Descripción | LVPECL FANOUT BUFFER | |
| Fabricantes | ICST | |
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Integrated
Circuit
Systems, Inc.
ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS8535-01 is a low skew, high performance
,&6 1-to-4 LVCMOS-to-3.3V LVPECL fanout buffer
HiPerClockS™ and a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8535-01 has two single ended clock inputs.
the single ended clock input accepts LVCMOS or LVTTL in-
put levels and translate them to 3.3V LVPECL levels. The
clock enable is internally synchronized to eliminate runt clock
pulses on the output during asynchronous assertion/
deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8535-01 ideal for those applications demand-
ing well defined performance and repeatability.
FEATURES
• 4 differential 3.3V LVPECL outputs
• Selectable CLK0 or CLK1 inputs for redundant
and multiple frequency fanout applications
• CLK0 or CLK1 can accept the following differential input
levels: LVCMOS or LVTTL
• Maximum output frequency up to 266MHz
• Translates LVCMOS and LVTTL levels to 3.3V
LVPECL levels
• Output skew: 30ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 1.9ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
CLK_EN
CLK0
CLK1
CLK_SEL
0
1
D
Q
LE
PIN ASSIGNMENT
VEE 1
20 Q0
CLK_EN 2 19 nQ0
CLK_SEL 3
18 VCC
CLK0 4 17 Q1
Q0 nc 5 16 nQ1
nQ0 CLK1 6 15 Q2
nc 7 14 nQ2
Q1
nQ1
nc 8
nc 9
13 VCC
12 Q3
Q2 VCC 10 11 nQ3
nQ2
ICS8535-01
Q3 20-Lead TSSOP
nQ3 4.4mm x 6.5mm x 0.92mm body package
G Package
Top View
ICS8535AG-01
www.icst.com/products/hiperclocks.html
1
REV. B JULY 5, 2001
1 page  
Integrated
Circuit
Systems, Inc.
ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
fMAX
tPD
tsk(o)
Maximum Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
IJ 266MHz
266
1.0 1.9
11 30
tsk(pp) Part-to-Part Skew; NOTE 3, 4
150
tR Output Rise Time
tF Output Fall Time
odc Output Duty Cycle
20% to 80% @ 50MHz
20% to 80% @ 50MHz
300
300
48
50
700
700
52
All parameters measured at 266MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 1: Measured from the 50% point of the input to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Uusing the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
ns
ps
ps
ps
ps
%
ICS8535AG-01
www.icst.com/products/hiperclocks.html
5
REV. B JULY 5, 2001
5 Page 
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX
ICS8535-01
LOW SKEW, 1-TO-4
LVCMOS-TO-3.3V LVPECL FANOUT BUFFER
ICS8535AG-01
TABLE 8. PACKAGE DIMENSIONS
SYMBOL
N
A
A1
A2
b
c
D
E
E1
e
L
α
aaa
Millimeters
MIN MAX
20
-- 1.20
0.05 0.15
0.80 1.05
0.19 0.30
0.09 0.20
6.40 6.60
6.40 BASIC
4.30 4.50
0.65 BASIC
0.45 0.75
0° 8°
-- 0.10
REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MO-153
www.icst.com/products/hiperclocks.html
11
REV. B JULY 5, 2001
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ICS8535-01.PDF ] | |
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