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Número de pieza | ICS8533-01 | |
Descripción | LVPECL FANOUT BUFFER | |
Fabricantes | ICST | |
Logotipo | ||
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Integrated
Circuit
Systems, Inc.
ICS8533-01
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS8533-01 is a low skew, high perfor-
,&6 mance 1-to-4 Differential-to-3.3V LVPECL fanout
HiPerClockS™ buffer and a member of the HiPerClockS™ family
of High Performance Clock Solutions from ICS.
The ICS8533-01 has two selectable clock inputs.
The CLK, nCLK pair can accept most standard differential
input levels. The PCLK, nPCLK pair can accept LVPECL, CML,
or SSTL input levels. The clock enable is internally synchro-
nized to eliminate runt pulses on the outputs during asynchro-
nous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8533-01 ideal for those applications demanding
well defined performance and repeatability.
FEATURES
• 4 differential 3.3V LVPECL outputs
• Selectable CLK, nCLK or LVPECL clock inputs
• CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, HSTL, SSTL, HCSL
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
• Maximum output frequency up to 650MHz
• Translates any single-ended input signal to 3.3V LVPECL
levels with resistor bias on nCLK input
• Output skew: 30ps (maximum)
• Part-to-part skew: 150ps (maximum)
• Propagation delay: 1.4ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
CLK_EN
CLK
nCLK
PCLK
nPCLK
CLK_SEL
0
1
D
Q
LE
PIN ASSIGNMENT
VEE 1
20 Q0
CLK_EN 2 19 nQ0
CLK_SEL 3
18 VCC
CLK 4 17 Q1
Q0 nCLK 5 16 nQ1
nQ0 PCLK 6 15 Q2
nPCLK 7 14 nQ2
Q1
nc 8
13 VCC
nQ1 nc 9 12 Q3
Q2 VCC 10 11 nQ3
nQ2
ICS8533-01
Q3 20-Lead TSSOP
nQ3 6.5mm x 4.4mm x 0.92mm Package Body
G Package
Top View
8533AG-01
www.icst.com/products/hiperclocks.html
1
REV. B JULY 16, 2001
1 page Integrated
Circuit
Systems, Inc.
ICS8533-01
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions Minimum Typical Maximum
PCLK
I Input High Current
IH nPCLK
VCC = VIN = 3.465V
VCC = VIN = 3.465V
PCLK
IIL
Input Low Current
nPCLK
VCC = 3.465V, VIN = 0V
V = 3.465V, V = 0V
CC IN
-5
-150
VPP Peak-to-Peak Input Voltage
0.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 1.5
VOH Output High Voltage; NOTE 3
VCC - 1.4
VOL Output Low Voltage; NOTE 3
VCC - 2.0
VSWING Peak-to-Peak Output Voltage Swing
0.6
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications the maximum input voltage for PCLK and nPCLK is VCC + 0.3V.
NOTE 3: Outputs terminated with 50Ω to VCC - 2V.
150
5
1
VCC
VCC - 1.0
VCC - 1.7
0.85
Units
µA
µA
µA
µA
V
V
V
V
V
TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
fMAX
tPD
tsk(o)
Maximum Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 5
IJ 650MHz
1.0
650
1.4
30
tsk(pp) Part-to-Part Skew; NOTE 3, 5
150
tjit(cc) Cycle to Cycle Jitter; NOTE 4, 5
150
tR Output Rise Time
tF Output Fall Time
odc Output Duty Cycle
20% to 80% @ 50MHz
20% to 80% @ 50MHz
300
300
47
700
700
53
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: The cycle to cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
ns
ps
ps
ps
ps
ps
%
8533AG-01
www.icst.com/products/hiperclocks.html
5
REV. B JULY 16, 2001
5 Page Integrated
Circuit
Systems, Inc.
ICS8533-01
LOW SKEW, 1-TO-4
DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W
200
98.0°C/W
66.6°C/W
500
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8533-01 is: 404
8533AG-01
www.icst.com/products/hiperclocks.html
11
REV. B JULY 16, 2001
11 Page |
Páginas | Total 13 Páginas | |
PDF Descargar | [ Datasheet ICS8533-01.PDF ] |
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