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PDF ICS85320I Data sheet ( Hoja de datos )
| Número de pieza | ICS85320I | |
| Descripción | LVPECL TRANSLATOR | |
| Fabricantes | ICST | |
| Logotipo |  |
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Integrated
Circuit
Systems, Inc.
ICS85320I
LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V / 3.3V LVPECL TRANSLATOR
GENERAL DESCRIPTION
ICS
The ICS85320I is a LVCMOS / LVTTL-to-Differ-
ential 2.5V / 3.3V LVPECL translator and a mem-
HiPerClockS™ ber of the HiPerClocks™family of High Perfor-
mance Clocks Solutions from ICS. The
ICS85320I has a single ended clock input. The
single ended clock input accepts LVCMOS or LVTTL input
levels and translates them to 2.5V / 3.3V LVPECL levels. The
small outline 8-pin SOIC package makes this device ideal for
applications where space, high performance and low power
are important.
FEATURES
• 1 differential 2.5V/3.3V LVPECL output
• LVCMOS/LVTTL CLK input
• CLK accepts the following input levels:
LVCMOS or LVTTL
• Maximum output frequency: 267MHz
• Part-to-part skew: 275ps (maximum)
• Additive phase jitter, RMS: 0.05ps (typical)
• 3.3V operating supply voltage
(operating range 3.135V to 3.465V)
• 2.5V operating supply voltage
(operating range 2.375V to 2.625V)
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
CLK
Q
nQ
PIN ASSIGNMENT
nc 1
Q2
nQ 3
nc 4
8 VCC
7 CLK
6 nc
5 VEE
ICS85320I
8-Lead SOIC
3.90mm x 4.92mm x 1.37mm body package
M Package
Top View
85320AMI
www.icst.com/products/hiperclocks.html
1
REV. A AUGUST 25, 2004
1 page  
Integrated
Circuit
Systems, Inc.
ICS85320I
LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V / 3.3V LVPECL TRANSLATOR
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental. This
ratio is expressed in decibels (dBm) or a ratio of the power in
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
Input/Output Additive Phase Jitter
@ 156.25MHz (12KHz to 20MHz)
= 0.05ps typical
10k
100k
1M
10M
OFFSET FROM CARRIER FREQUENCY (HZ)
100M
As with most timing specifications, phase noise measurements
have issues. The primary issue relates to the limitations of the
equipment. Often the noise floor of the equipment is higher than
the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be
lower. The phase noise is dependant on the input source and
measurement equipment.
85320AMI
www.icst.com/products/hiperclocks.html
5
REV. A AUGUST 25, 2004
5 Page 
Integrated
Circuit
Systems, Inc.
ICS85320I
LVCMOS / LVTTL-TO-DIFFERENTIAL
2.5V / 3.3V LVPECL TRANSLATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
• For logic high, V = V = V
– 1.0V
OUT
OH_MAX
CCO_MAX
(V - V ) = 1.0V
CCO_MAX OH_MAX
• For logic low, V = V = V
– 1.7V
OUT
OL_MAX
CCO_MAX
(V - V ) = 1.7V
CCO_MAX OL_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V – (V
- 2V))/R ] * (V
- V ) = [(2V - (V
- V ))/R ] * (V
-V )=
OH_MAX
CCO_MAX
L CCO_MAX OH_MAX
CCO_MAX OH_MAX
L
CCO_MAX OH_MAX
[(2V - 1V)/50Ω] * 1V = 20.0mW
Pd_L = [(V – (V
- 2V))/R ] * (V
- V ) = [(2V - (V
- V ))/R ] * (V
-V )=
OL_MAX
CCO_MAX
L CCO_MAX OL_MAX
CCO_MAX OL_MAX
L
CCO_MAX OL_MAX
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
85320AMI
www.icst.com/products/hiperclocks.html
11
REV. A AUGUST 25, 2004
11 Page | ||
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| PDF Descargar | [ Datasheet ICS85320I.PDF ] | |
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