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PDF ICS85314-01 Data sheet ( Hoja de datos )
| Número de pieza | ICS85314-01 | |
| Descripción | LVPECL FANOUT BUFFER | |
| Fabricantes | ICST | |
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Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS85314-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS85314-01 is a low skew, high performance
,&6 1-to-5 Differential-to-3.3V LVPECL fanout buffer
HiPerClockS™ and a member of the HiPerClockS™ family of
High Performance Clock Solutions from ICS.
The ICS85314-01 has two selectable clock inputs.
The CLK0, nCLK0 pair can accept most standard differential
input levels. The single-ended CLK1 can accept LVCMOS or
LVTTL input levels. The clock enable is internally synchronized
to eliminate runt clock pulses on the outputs during asynchro-
nous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make
the ICS85314-01 ideal for those applications demanding well
defined performance and repeatability.
FEATURES
• 5 differential 2.5V/3.3V LVPECL outputs
• Selectable differential CLK0, nCLK0 or LVCMOS inputs
• CLK0, nCLK0 pair can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
• CLK1 can accept the following input levels:
LVCMOS or LVTTL
• Maximum output frequency: 650MHz
• Translates any single-ended input signal to 3.3V LVPECL
levels with resistor bias on nCLK input
• Output skew: 50ps (maximum)
• Part-to-part skew: 400ps (maximum)
• Propagation delay: CLK0, nCLK0 - 2.1ns (maximum)
CLK1 - 2.1ns (maximum)
• LVPECL mode operating voltage supply range:
V = 2.375V to 3.8V, V = 0V
CC EE
• -40°C to 85°C ambient operating temperature
• Compatible to part number MC100LVEL14
BLOCK DIAGRAM
nCLK_EN
CLK0
nCLK0
CLK1
CLK_SEL
00
11
D
Q
LE
PIN ASSIGNMENT
Q0 1
20 VCC
nQ0 2 19 nCLK_EN
Q1 3
18 VCC
nQ1 4
17 nc
Q0
Q2 5
16 CLK1
nQ0
nQ2 6
15 CLK0
Q1
nQ1
Q3 7
nQ3 8
Q4 9
14 nCLK0
13 nc
12 CLK_SEL
Q2 nQ4 10 11 VEE
nQ2
ICS85314-01
Q3 20-Lead TSSOP
nQ3 6.5mm x 4.4mm x 0.92mm Package Body
Q4 G Package
nQ4 Top View
ICS85314-01
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm Package Body
M Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
85314AG-01
www.icst.com/products/hiperclocks.html
REV. B JUNE 21, 2002
1
1 page  
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS85314-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = 2.375V TO 3.8V, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions Minimum Typical
VOH Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1
VSWING Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
VCC - 1.4
VCC - 2.0
0.6
Maximum
VCC - 1.0
VCC - 1.7
1.0
Units
V
V
V
TABLE
5.
AC
CHARACTERISTICS,
V=
CC
2.375V
TO
3.8V,
V
EE
=
0V,
TA
=
-40°C
TO
85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f Output Frequency
MAX
CLK0, nCLK0;
tpLH
Propagation Delay,
Low to High
NOTE 1
CLK1; NOTE 2
IJ 650MHz
IJ 250MHz
1.0
1.0
650 MHz
2.1 ns
2.1 ns
tsk(o) Output Skew; NOTE 3, 5
50 ps
tsk(pp) Part-to-Part Skew; NOTE 4, 5
400 ps
tR Output Rise Time
20% to 80% @ 50MHz
tF Output Fall Time
20% to 80% @ 50MHz
CLK0, nCLK0
odc Output Duty Cycle
CLK1
IJ 650MHz
IJ 250MHz
200
200
45
45
All parameters measured at 250MHz unless noted otherwise.
The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Measured from VCC/2 input crossing point to the differential output crossing point.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
700
700
55
55
ps
ps
%
%
85314AG-01
www.icst.com/products/hiperclocks.html
5
REV. B JUNE 21, 2002
5 Page 
Integrated
Circuit
Systems, Inc.
PRELIMINARY
ICS85314-01
LOW SKEW, 1-TO-5
DIFFERENTIAL-TO-2.5V/3.3V LVPECL FANOUT BUFFER
3. Calculations and Equations.
LVPECL output driver circuit and termination are shown in Figure 4.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 4 - LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
• For logic high, V = V = V – 1.0V
OUT
OH_MAX
CC_MAX
(V - V ) = 1.0V
CC_MAX OH_MAX
• For logic low, V = V = V – 1.7V
OUT
OL_MAX
CC_MAX
(V - V ) = 1.7V
CC_MAX OL_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V – (V - 2V))/R ] * (V - V ) = [(2V - (V
- V ))/R ] * (V - V ) =
OH_MAX
CC_MAX
L CC_MAX OH_MAX
CC_MAX OH_MAX
L
CC_MAX OH_MAX
[(2V - 1V)/50Ω] * 1V = 20.0mW
Pd_L = [(V – (V
- 2V))/R ] * (V
- V ) = [(2V - (V
- V ))/R ] * (V
-V )=
OL_MAX
CC_MAX
L CC_MAX OL_MAX
CC_MAX
OL_MAX
L
CC_MAX OL_MAX
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
85314AG-01
www.icst.com/products/hiperclocks.html
11
REV. B JUNE 21, 2002
11 Page | ||
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| PDF Descargar | [ Datasheet ICS85314-01.PDF ] | |
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