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PDF ICS853111A Data sheet ( Hoja de datos )
| Número de pieza | ICS853111A | |
| Descripción | LVPECL/ECL FANOUT BUFFER | |
| Fabricantes | ICST | |
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Integrated
Circuit
Systems, Inc.
ICS853111A
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS853111A is a low skew, high perfor-
ICS mance 1-to-10 Differential-to-2.5V/3.3V LVPECL/
HiPerClockS™ ECL Fanout Buffer and a member of the
HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS853111A
is characterized to operate from either a 2.5V, 3.3V or a
5V power supply. Guaranteed output and par t-to-par t
skew characteristics make the ICS853111A ideal for
those clock distribution applications demanding well de-
fined performance and repeatability.
FEATURES
• 10 differential 2.5V/3.3V LVPECL / ECL outputs
• 2 selectable differential input pairs
• PCLKx, nPCLKx pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: >3GHz
• Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nPCLK input
• Output skew: 23ps (typical)
• Part-to-part skew: 85ps (typical)
• Propagation delay: 705ps (typical)
• Jitter, RMS: < 0.03ps (typical)
• LVPECL mode operating voltage supply range:
V = 2.375V to 5.25V, V = 0V
CC EE
• ECL mode operating voltage supply range:
VCC = 0V, VEE = -5.25V to -2.375V
• -40°C to 85°C ambient operating temperature
• Pin compatible with MC100EP111 and MC100LVEP111
BLOCK DIAGRAM
PCLK0
nPCLK0
PCLK1
nPCLK1
0
1
CLK_SEL
V
BB
853111AY
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
24 23 22 21 20 19 18 17
Q2
nQ2
VCCO
nQ2
Q2
25
26
27
1 6 VCCO
15 Q7
14 nQ7
Q3
nQ3
nQ1 28 ICS853111A 13 Q8
Q1 29
12 nQ8
Q4
nQ4
nQ0
Q0
30
31
11 Q9
10 nQ9
Q5
nQ5
VCCO 3 2
9 VCCO
123456 78
Q6
nQ6
Q7
nQ7
Q8 32-Lead LQFP
nQ8 7mm x 7mm x 1.4mm package body
Y Package
Q9 Top View
nQ9
www.icst.com/products/hiperclocks.html
1
REV. B MAY 14, 2004
1 page  
Integrated
Circuit
Systems, Inc.
ICS853111A
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
TABLE 4C. ECL DC CHARACTERISTICS, VCC = 0V; VEE = -5.25V TO -2.375V
Symbol Parameter
-40°C
Min Typ Max Min
25°C
Typ
Max
85°C
Units
Min Typ Max
VOH
VOL
VIH
VIL
V
BB
VPP
VCMR
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Input High Voltage(Single-Ended)
Input Low Voltage(Single-Ended)
Output Voltage Reference; NOTE 2
Peak-to-Peak Input Voltage
Input High Voltage
Common Mode Range; NOTE 3, 4
-1.125
-1.895
-1.225
-1.87
-1.44
150
VEE+1.2V
-1.025
-1.755
800
-0.92
-1.62
-0.94
-1.535
-1.32
1200
0
-1.075
-1.875
-1.225
-1.87
-1.44
150
VEE+1.2V
-1.005
-1.78
800
-0.93
-1.685
-0.94
-1.535
-1.32
1200
0
-1.005
-1.86
-1.225
-1.87
-1.44
150
VEE+1.2V
-0.97
-1.765
800
-0.935
-1.67
-0.94
-1.535
-1.32
1200
0
V
V
V
V
V
mV
V
IIH
Input
PCLK0, PCLK1
High Current nPCLK0, nPCLK1
150 150 150 µA
IIL
Input
PCLK0, PCLK1
Low Current nPCLK0, nPCLK1
-10
-150
-10
-150
-10
-150
Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode.
NOTE 3: Common mode voltage is defined as VIH.
NOTE 4: For single-ended applications, the maximum input voltage for PCLK0, nPCLK0 and PCLK1, nPCLK1
is VCC + 0.3V.
µA
µA
TABLE
5.
AC
CHARACTERISTICS,
V
CC
=
0V;
V
EE
=
-5.25V
TO
-2.375V
OR
V
CC
=
2.375V
TO
5.25V;
V
EE
=
0V
Symbol Parameter
-40°C
25°C
85°C
Min Typ Max Min Typ Max Min Typ Max
fMAX
tPD
tsk(o)
Output Frequency
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
>3 >3 >3
570 670 770 605 705 805 665 765 875
23 35
23 35
23 35
tsk(pp)
tjit
Part-to-Part Skew; NOTE 3, 4
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section
85 150
0.03
85 150
0.03
85 150
0.03
tR/tF Output Rise/Fall Time 20% to 80% 85 200 315 100 200 285 85 200
All parameters are measured ≤ 1GHz unless otherwise noted.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at the differential cross points.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
315
Units
GHz
ps
ps
ps
ps
ps
853111AY
www.icst.com/products/hiperclocks.html
5
REV. B MAY 14, 2004
5 Page 
Integrated
Circuit
Systems, Inc.
ICS853111A
LOW SKEW, 1-TO-10
DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both VSWING and VOH must meet the VPP
and VCMR input requirements. Figures 5A to 5F show interface
examples for the HiPerClockS PCLK/nPCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. If the driver is from another vendor,
use their termination recommendation. Please consult with
the vendor of the driver component to confirm the driver ter-
mination requirements.
3.3V
CML
Zo = 50 Ohm
Zo = 50 Ohm
3.3V
R1 R2
50 50
3.3V
PCLK
nPCLK HiPerClockS
PCLK/nPCLK
3.3V
Zo = 50 Ohm
3.3V
R1 PCLK
100
nPCLK
Zo = 50 Ohm
HiPerClockS
CML Built-In Pullup
PCLK/nPCLK
FIGURE 5A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN OPEN COLLECTOR CML DRIVER
FIGURE 5B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A BUILT-IN PULLUP CML DRIVER
3.3V
Zo = 50 Ohm
LVPEC L
Zo = 50 Ohm
3. 3V
R3 R4
125 125
3.3V
PCLK
nPCLK HiPerClockS
Input
R1 R2
84 84
3.3V
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
3.3V
R3 R4
84
C1
84
C2
R5
100 - 200
R6
100 - 200
R1 R2
125 125
3.3V
PCLK
nPCLK HiPerClockS
PCLK/nPCLK
FIGURE 5C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 5D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
2.5V
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
2.5V
R3 R4
120 120
3.3V
PCLK
R1 R2
120 120
nPCLK
HiPerClockS
PCLK/nPCLK
3.3V
LVDS
Zo = 50 Ohm
Zo = 50 Ohm
R5
100
3.3V
3.3V
R3 R4
1K 1K
C1
PCLK
C2
nPCLK
HiPerClockS
PC L K / n PC L K
R1 R2
1K 1K
FIGURE 5E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
FIGURE 5F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
853111AY
www.icst.com/products/hiperclocks.html
11
REV. B MAY 14, 2004
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ICS853111A.PDF ] | |
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